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Searched refs:HasV5TEOps (Results 1 – 15 of 15) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARM.td107 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
112 [HasV5TEOps]>;
168 def : ProcNoItin<"arm9e", [HasV5TEOps]>;
169 def : ProcNoItin<"arm926ej-s", [HasV5TEOps]>;
170 def : ProcNoItin<"arm946e-s", [HasV5TEOps]>;
171 def : ProcNoItin<"arm966e-s", [HasV5TEOps]>;
172 def : ProcNoItin<"arm968e-s", [HasV5TEOps]>;
173 def : ProcNoItin<"arm10e", [HasV5TEOps]>;
174 def : ProcNoItin<"arm1020e", [HasV5TEOps]>;
175 def : ProcNoItin<"arm1022e", [HasV5TEOps]>;
[all …]
DARMSubtarget.h43 bool HasV5TEOps; variable
190 bool hasV5TEOps() const { return HasV5TEOps; } in hasV5TEOps()
DARMSubtarget.cpp44 , HasV5TEOps(false) in ARMSubtarget()
98 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; in ARMSubtarget()
DARMInstrInfo.td173 AssemblerPredicate<"HasV5TEOps">;
/external/llvm/lib/Target/ARM/
DARMSubtarget.h89 bool HasV5TEOps = false; variable
395 bool hasV5TEOps() const { return HasV5TEOps; } in hasV5TEOps()
DARM.td274 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
279 [HasV5TEOps]>;
384 def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
386 def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
DARMInstrInfo.td193 AssemblerPredicate<"HasV5TEOps", "armv5te">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMSubtarget.h145 bool HasV5TEOps = false; variable
521 bool hasV5TEOps() const { return HasV5TEOps; } in hasV5TEOps()
DARM.td388 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
395 [HasV5TEOps]>;
531 def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
533 def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
DARMInstrInfo.td225 AssemblerPredicate<"HasV5TEOps", "armv5te">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMTargetStreamer.cpp142 else if (STI.hasFeature(ARM::HasV5TEOps)) in getArchForCPU()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenSubtargetInfo.inc120 HasV5TEOps = 104,
203 { "armv5te", "ARMv5te architecture", { ARM::ARMv5te }, { ARM::HasV5TEOps } },
204 { "armv5tej", "ARMv5tej architecture", { ARM::ARMv5tej }, { ARM::HasV5TEOps } },
300 …{ "v5te", "Support ARM v5TE, v5TEj, and v5TExp instructions", { ARM::HasV5TEOps }, { ARM::HasV5TOp…
301 { "v6", "Support ARM v6 instructions", { ARM::HasV6Ops }, { ARM::HasV5TEOps } },
16599 if (Bits[ARM::HasV5TEOps]) HasV5TEOps = true;
DARMGenMCCodeEmitter.inc11187 if ((FB[ARM::HasV5TEOps]))
DARMGenDisassemblerTables.inc11217 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV5TEOps]);
DARMGenAsmMatcher.inc7637 if ((FB[ARM::HasV5TEOps]))