| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARM.td | 110 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
115 [HasV6Ops, FeatureThumb2]>;
180 def : Processor<"arm1136j-s", ARMV6Itineraries, [HasV6Ops]>;
181 def : Processor<"arm1136jf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
183 def : Processor<"arm1176jz-s", ARMV6Itineraries, [HasV6Ops]>;
184 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
186 def : Processor<"mpcorenovfp", ARMV6Itineraries, [HasV6Ops]>;
187 def : Processor<"mpcore", ARMV6Itineraries, [HasV6Ops, FeatureVFP2,
191 def : Processor<"cortex-m0", ARMV6Itineraries, [HasV6Ops, FeatureNoARM,
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| D | ARMSubtarget.cpp | 45 , HasV6Ops(false) in ARMSubtarget()
98 HasV4TOps = HasV5TOps = HasV5TEOps = HasV6Ops = HasV6T2Ops = true; in ARMSubtarget()
115 IsR9Reserved = ReserveR9 | !HasV6Ops; in ARMSubtarget()
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| D | ARMSubtarget.h | 44 bool HasV6Ops; variable
191 bool hasV6Ops() const { return HasV6Ops; } in hasV6Ops()
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| D | ARMInstrInfo.td | 175 AssemblerPredicate<"HasV6Ops">;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.h | 90 bool HasV6Ops = false; variable
396 bool hasV6Ops() const { return HasV6Ops; } in hasV6Ops()
557 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9; in isR9Reserved()
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| D | ARM.td | 277 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
282 [HasV6Ops]>;
288 [HasV6Ops]>;
388 def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
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| D | ARMInstrInfo.td | 195 AssemblerPredicate<"HasV6Ops", "armv6">;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.h | 146 bool HasV6Ops = false; variable
522 bool hasV6Ops() const { return HasV6Ops; } in hasV6Ops()
704 return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9; in isR9Reserved()
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| D | ARM.td | 393 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
399 [HasV6Ops]>;
407 [HasV6Ops]>;
535 def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops,
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| D | ARMInstrInfo.td | 227 AssemblerPredicate<"HasV6Ops", "armv6">;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMTargetStreamer.cpp | 140 else if (STI.hasFeature(ARM::HasV6Ops)) in getArchForCPU()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenSubtargetInfo.inc | 124 HasV6Ops = 108,
205 { "armv6", "ARMv6 architecture", { ARM::ARMv6 }, { ARM::HasV6Ops, ARM::FeatureDSP } },
301 { "v6", "Support ARM v6 instructions", { ARM::HasV6Ops }, { ARM::HasV5TEOps } },
302 { "v6k", "Support ARM v6k instructions", { ARM::HasV6KOps }, { ARM::HasV6Ops } },
303 { "v6m", "Support ARM v6M instructions", { ARM::HasV6MOps }, { ARM::HasV6Ops } },
16603 if (Bits[ARM::HasV6Ops]) HasV6Ops = true;
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| D | ARMGenDisassemblerTables.inc | 11213 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV6Ops]);
11273 return (Bits[ARM::ModeThumb] && Bits[ARM::HasV6Ops]);
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| D | ARMGenMCCodeEmitter.inc | 11189 if ((FB[ARM::HasV6Ops]))
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| D | ARMGenAsmMatcher.inc | 7639 if ((FB[ARM::HasV6Ops]))
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 115 return STI.getFeatureBits() & ARM::HasV6Ops; in hasV6Ops()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 454 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 264 return getSTI().getFeatureBits()[ARM::HasV6Ops]; in hasV6Ops()
|