Searched refs:HasV8_4aOps (Results 1 – 19 of 19) sorted by relevance
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenSystemOperands.inc | 1687 { "DIT", 0x1A, {AArch64::HasV8_4aOps} }, // 5 2630 { "VSTCR_EL2", 0xE132, true, true, {AArch64::HasV8_4aOps} }, // 648 2631 { "VSTTBR_EL2", 0xE130, true, true, {AArch64::HasV8_4aOps} }, // 649 2632 { "CNTHVS_TVAL_EL2", 0xE720, true, true, {AArch64::HasV8_4aOps} }, // 650 2633 { "CNTHVS_CVAL_EL2", 0xE722, true, true, {AArch64::HasV8_4aOps} }, // 651 2634 { "CNTHVS_CTL_EL2", 0xE721, true, true, {AArch64::HasV8_4aOps} }, // 652 2635 { "CNTHPS_TVAL_EL2", 0xE728, true, true, {AArch64::HasV8_4aOps} }, // 653 2636 { "CNTHPS_CVAL_EL2", 0xE72A, true, true, {AArch64::HasV8_4aOps} }, // 654 2637 { "CNTHPS_CTL_EL2", 0xE729, true, true, {AArch64::HasV8_4aOps} }, // 655 2638 { "SDER32_EL2", 0xE099, true, true, {AArch64::HasV8_4aOps} }, // 656 [all …]
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D | AArch64GenAsmWriter.inc | 17510 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 17524 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 17538 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 17552 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 17566 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 17580 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 17594 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 17608 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 17622 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 22648 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { [all …]
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D | AArch64GenAsmWriter1.inc | 18198 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 18212 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 18226 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 18240 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 18254 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 18268 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 18282 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 18296 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 18310 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { 23336 STI.getFeatureBits()[AArch64::HasV8_4aOps]) { [all …]
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D | AArch64GenSubtargetInfo.inc | 63 HasV8_4aOps = 47, 159 …{ "v8.4a", "Support ARM v8.4a instructions", { AArch64::HasV8_4aOps }, { AArch64::HasV8_3aOps, AAr… 10939 if (Bits[AArch64::HasV8_4aOps]) HasV8_4aOps = true;
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D | AArch64GenMCCodeEmitter.inc | 12020 if ((FB[AArch64::HasV8_4aOps]))
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D | AArch64GenDisassemblerTables.inc | 17673 return (Bits[AArch64::HasV8_4aOps]);
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D | AArch64GenAsmMatcher.inc | 11745 if ((FB[AArch64::HasV8_4aOps]))
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64Subtarget.h | 69 bool HasV8_4aOps = false; variable 213 bool hasV8_4aOps() const { return HasV8_4aOps; } in hasV8_4aOps()
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D | AArch64.td | 212 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
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D | AArch64SystemOperands.td | 157 code Requires = [{ {AArch64::HasV8_4aOps} }]; 299 let Requires = [{ {AArch64::HasV8_4aOps} }] in 370 let Requires = [{ {AArch64::HasV8_4aOps} }] in { 1200 let Requires = [{ {AArch64::HasV8_4aOps} }] in { 1318 } // HasV8_4aOps
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D | AArch64InstrInfo.td | 24 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMSubtarget.h | 155 bool HasV8_4aOps = false; variable 531 bool hasV8_4aOps() const { return HasV8_4aOps; } in hasV8_4aOps()
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D | ARM.td | 439 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 648 def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps,
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D | ARMInstrInfo.td | 257 AssemblerPredicate<"HasV8_4aOps", "armv8.4a">;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 2733 else if (FBS[AArch64::HasV8_4aOps]) in setRequiredFeatureString()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenSubtargetInfo.inc | 133 HasV8_4aOps = 117, 226 …{ "armv8.4-a", "ARMv84a architecture", { ARM::ARMv84a }, { ARM::HasV8_4aOps, ARM::FeatureAClass, A… 311 …{ "v8.4a", "Support ARM v8.4a instructions", { ARM::HasV8_4aOps }, { ARM::HasV8_3aOps, ARM::Featur… 16612 if (Bits[ARM::HasV8_4aOps]) HasV8_4aOps = true;
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D | ARMGenDisassemblerTables.inc | 11239 return (!Bits[ARM::ModeThumb] && Bits[ARM::HasV8_4aOps]); 11305 return (Bits[ARM::ModeThumb] && Bits[ARM::HasV8_4aOps]);
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D | ARMGenMCCodeEmitter.inc | 11213 if ((FB[ARM::HasV8_4aOps]))
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D | ARMGenAsmMatcher.inc | 7663 if ((FB[ARM::HasV8_4aOps]))
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