| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 101 void HexagonInstrInfo::anchor() {} in anchor()
103 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) in HexagonInstrInfo() function in HexagonInstrInfo
234 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
301 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
373 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()
544 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { in RemoveBranch()
564 unsigned HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB, in InsertBranch()
665 bool HexagonInstrInfo::analyzeLoop(MachineLoop &L, in analyzeLoop()
683 unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB, in reduceLoopCount()
740 bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, in isProfitableToIfCvt()
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| D | HexagonFrameLowering.h | 19 class HexagonInstrInfo; variable
86 void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
102 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
105 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
108 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
111 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
114 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
117 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
120 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
123 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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| D | HexagonBitTracker.h | 17 class HexagonInstrInfo; variable
27 const HexagonInstrInfo &tii, MachineFunction &mf);
38 const HexagonInstrInfo &TII;
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| D | HexagonSubtarget.h | 52 HexagonInstrInfo InstrInfo;
68 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
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| D | HexagonFixupHwLoops.cpp | 113 const HexagonInstrInfo *HII = in fixupLoopInstrs()
114 static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in fixupLoopInstrs()
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| D | HexagonNewValueJump.cpp | 67 const HexagonInstrInfo *QII;
112 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, in INITIALIZE_PASS_DEPENDENCY()
214 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, in canCompareBeNewValueJump()
402 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| D | Hexagon.td | 251 include "HexagonInstrInfo.td"
255 def HexagonInstrInfo : InstrInfo;
290 let InstructionSet = HexagonInstrInfo;
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| D | HexagonPeephole.cpp | 84 const HexagonInstrInfo *QII;
118 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| D | HexagonInstrInfo.h | 31 class HexagonInstrInfo : public HexagonGenInstrInfo {
36 explicit HexagonInstrInfo(HexagonSubtarget &ST);
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| D | CMakeLists.txt | 34 HexagonInstrInfo.cpp
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| D | HexagonBitSimplify.cpp | 179 uint16_t Begin, const HexagonInstrInfo &HII);
575 BitVector &Bits, uint16_t Begin, const HexagonInstrInfo &HII) { in getUsedBits()
913 const HexagonInstrInfo &HII;
1001 RedundantInstrElimination(BitTracker &bt, const HexagonInstrInfo &hii, in RedundantInstrElimination()
1015 const HexagonInstrInfo &HII;
1316 ConstGeneration(BitTracker &bt, const HexagonInstrInfo &hii, in ConstGeneration()
1326 const HexagonInstrInfo &HII;
1459 CopyGeneration(BitTracker &bt, const HexagonInstrInfo &hii, in CopyGeneration()
1467 const HexagonInstrInfo &HII;
1661 BitSimplification(BitTracker &bt, const HexagonInstrInfo &hii, in BitSimplification()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 116 void HexagonInstrInfo::anchor() {} in anchor()
118 HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) in HexagonInstrInfo() function in HexagonInstrInfo
147 MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB, in findLoopInstr()
240 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
288 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
338 bool HexagonInstrInfo::hasLoadFromStackSlot(const MachineInstr &MI, in hasLoadFromStackSlot()
356 bool HexagonInstrInfo::hasStoreToStackSlot(const MachineInstr &MI, in hasStoreToStackSlot()
386 bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()
556 unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB, in removeBranch()
579 unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, in insertBranch()
[all …]
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| D | HexagonFrameLowering.h | 24 class HexagonInstrInfo; variable
109 void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII,
128 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
131 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
134 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
137 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
140 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
143 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
146 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
149 MachineRegisterInfo &MRI, const HexagonInstrInfo &HII,
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| D | HexagonBitTracker.h | 19 class HexagonInstrInfo; variable
33 const HexagonInstrInfo &tii, MachineFunction &mf);
49 const HexagonInstrInfo &TII;
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| D | HexagonSubtarget.h | 77 bool shouldTFRICallBind(const HexagonInstrInfo &HII,
86 HexagonInstrInfo InstrInfo;
102 const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
262 bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
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| D | HexagonHazardRecognizer.h | 25 const HexagonInstrInfo *TII;
46 const HexagonInstrInfo *HII, in HexagonHazardRecognizer()
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| D | HexagonSubtarget.cpp | 148 auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII); in apply()
182 const HexagonInstrInfo &HII, const SUnit &Inst1, in shouldTFRICallBind()
268 const auto &HII = static_cast<const HexagonInstrInfo&>(*DAG->TII); in apply()
327 const HexagonInstrInfo *QII = getInstrInfo(); in adjustSchedDependency()
412 auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo()); in updateLatency()
488 const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc, in isBestZeroLatency()
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| D | HexagonVLIWPacketizer.h | 20 class HexagonInstrInfo; variable
67 const HexagonInstrInfo *HII;
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| D | HexagonFixupHwLoops.cpp | 113 const HexagonInstrInfo *HII = in fixupLoopInstrs()
114 static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in fixupLoopInstrs()
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| D | HexagonISelDAGToDAG.h | 27 class HexagonInstrInfo; variable
33 const HexagonInstrInfo *HII;
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| D | HexagonNewValueJump.cpp | 96 const HexagonInstrInfo *QII;
117 static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, in INITIALIZE_PASS_DEPENDENCY()
238 static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII, in canCompareBeNewValueJump()
460 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| D | HexagonVectorPrint.cpp | 55 const HexagonInstrInfo *QII = nullptr;
98 const DebugLoc &DL, const HexagonInstrInfo *QII, in addAsmInstr()
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| D | HexagonPeephole.cpp | 83 const HexagonInstrInfo *QII;
114 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | tail-dup-subreg-abort.ll | 6 ; This could lead to HexagonInstrInfo::copyPhysReg aborting on an unhandled
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | tail-dup-subreg-abort.ll | 6 ; This could lead to HexagonInstrInfo::copyPhysReg aborting on an unhandled
|