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Searched refs:HiOpc (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonCopyToCombine.cpp187 unsigned HiOpc = HighRegInst.getOpcode(); in areCombinableOperations() local
200 verifyOpc(HiOpc); in areCombinableOperations()
203 if (HiOpc == Hexagon::V6_vassign || LoOpc == Hexagon::V6_vassign) in areCombinableOperations()
204 return HiOpc == LoOpc; in areCombinableOperations()
/external/llvm/lib/Target/Hexagon/
DHexagonCopyToCombine.cpp187 unsigned HiOpc = HighRegInst.getOpcode(); in areCombinableOperations() local
189 (void)HiOpc; // Fix compiler warning in areCombinableOperations()
191 assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) && in areCombinableOperations()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.h93 unsigned LoOpc, unsigned HiOpc,
DMipsSEInstrInfo.cpp557 unsigned HiOpc, in expandPseudoMTLoHi() argument
568 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); in expandPseudoMTLoHi()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.h96 unsigned LoOpc, unsigned HiOpc,
DMipsSEInstrInfo.cpp715 unsigned HiOpc, in expandPseudoMTLoHi() argument
726 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); in expandPseudoMTLoHi()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp4270 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64; in splitScalar64BitAddSub() local
4272 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1) in splitScalar64BitAddSub()
DSIISelLowering.cpp3276 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32; in EmitInstrWithCustomInserter() local
3280 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter()