Searched refs:HiRegList (Results 1 – 3 of 3) sorted by relevance
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMCallingConv.h | 75 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS() local 79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); in f64AssignAAPCS() 94 if (HiRegList[i] == Reg) in f64AssignAAPCS() 121 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign() local 124 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); in f64RetAssign() 130 if (HiRegList[i] == Reg) in f64RetAssign()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMCallingConv.h | 74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS() local 79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS() 99 if (HiRegList[i] == Reg) in f64AssignAAPCS() 126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign() local 129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign() 135 if (HiRegList[i] == Reg) in f64RetAssign()
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/external/llvm/lib/Target/ARM/ |
D | ARMCallingConv.h | 74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64AssignAAPCS() local 79 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList); in f64AssignAAPCS() 99 if (HiRegList[i] == Reg) in f64AssignAAPCS() 126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 }; in f64RetAssign() local 129 unsigned Reg = State.AllocateReg(HiRegList, LoRegList); in f64RetAssign() 135 if (HiRegList[i] == Reg) in f64RetAssign()
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