Home
last modified time | relevance | path

Searched refs:I2C (Results 1 – 25 of 146) sorted by relevance

123456

/external/u-boot/drivers/i2c/
DKconfig2 # I2C subsystem configuration
5 menu "I2C support"
8 bool "Enable Driver Model for I2C drivers"
11 Enable driver model for I2C. The I2C uclass interface: probe, read,
20 bool "Enable I2C compatibility layer"
23 Enable old-style I2C functions for compatibility with existing code.
29 tristate "Chrome OS EC tunnel I2C bus"
32 This provides an I2C bus that will tunnel i2c commands through to
33 the other side of the Chrome OS EC to the I2C bus connected there.
35 I2C or LPC). Some Chromebooks use this when the hardware design
[all …]
/external/u-boot/drivers/i2c/muxes/
DKconfig2 bool "Support I2C multiplexers"
5 This enables I2C buses to be multiplexed, so that you can select
8 using a suitable I2C MUX driver.
11 bool "Support I2C multiplexers on SPL"
14 This enables I2C buses to be multiplexed, so that you can select
17 using a suitable I2C MUX driver.
20 bool "GPIO-based I2C arbitration"
24 I2C multimaster arbitration scheme using GPIOs and a challenge &
29 tristate "TI PCA954x I2C Mux/switches"
33 I2C mux/switch devices. It is x width I2C multiplexer which enables to
[all …]
/external/u-boot/doc/
DI2C_Edge_Conditions1 I2C Edge Conditions:
4 I2C devices may be left in a write state if a read was occuring
9 2) I2C controller issues a start command.
10 3) The I2C writes the device address.
14 1) The I2C controller issues a start command.
15 2) The I2C controller writes the device address.
16 3) The I2C controller writes the offset.
31 !!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A AMCC 4xx BUG!!!
33 This reset edge condition could possibly be present in every I2C
34 controller and device available. For boards where a I2C bus reset
[all …]
DREADME.i2c1 I2C Bus Arbitration
4 While I2C supports multi-master buses this is difficult to get right.
6 Clock-stretching and the arbitrary time that an I2C transaction can take
22 The driver is implemented as an I2C mux, as it is in Linux. See
/external/u-boot/doc/device-tree-bindings/i2c/
Dnvidia,tegra186-bpmp-i2c.txt1 NVIDIA Tegra186 BPMP I2C controller
4 devices, such as the I2C controller for the power management I2C bus. Software
6 transactions on that I2C bus. This binding describes an I2C bus that is
9 The BPMP I2C node must be located directly inside the main BPMP node. See
12 This node represents an I2C controller. See ../i2c/i2c.txt for details of the
13 core I2C binding.
20 - #address-cells: Address cells for I2C device address.
28 Indicates the I2C bus number this DT node represent, as defined by the
Di2c.txt1 U-Boot I2C
4 U-Boot's I2C model has the concept of an offset within a chip (I2C target
9 Apart from the controller-specific I2C bindings, U-Boot supports a special
19 Pin description for I2C bus software deblocking.
Di2c-stm32.txt1 * I2C controller embedded in STMicroelectronis STM32 platforms
7 - clocks: Must contain the input clock of the I2C instance
9 operation for I2C transfer
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
Di2c-cdns.txt1 Cadence I2C controller Device Tree Bindings
6 - reg : Physical base address and size of I2C registers map.
Di2c-at91.txt1 I2C for Atmel platforms
14 - clock-frequency: Desired I2C bus frequency in Hz, default value is 100000.
Dtegra20-i2c.txt8 - the I2C clock to use for the peripheral
10 does not change and is the same for all I2C nodes.
/external/u-boot/drivers/misc/
DKconfig27 Enable support for I2C connected Atmel's ATSHA204A
52 and talking to the I2C bus behind the EC (if there is one).
64 bool "Enable Chrome OS EC I2C driver"
67 Enable I2C access to the Chrome OS EC. This is used on older
69 changed to SPI. The EC will accept commands across the I2C using
76 Enable I2C access to the Chrome OS EC. This is used on x86
96 provides a faster and more robust interface than I2C but the bugs
105 connected over I2C.
152 is connected via I2C. So I2C needs to be enabled.
155 hex "I2C address of PCA9551 LED controller"
[all …]
/external/apache-commons-bcel/src/main/java/org/apache/bcel/generic/
DI2C.java26 public class I2C extends ConversionInstruction { class
30 public I2C() { in I2C() method in I2C
31 super(org.apache.bcel.Const.I2C); in I2C()
/external/u-boot/board/ti/common/
DKconfig5 Evaluation Boards which have I2C based EEPROM detection
8 int "Board EEPROM's I2C bus address"
13 hex "Board EEPROM's I2C chip address"
/external/u-boot/doc/driver-model/
Di2c-howto.txt4 Over half of the I2C drivers have been converted as at November 2016. These
23 Here is a suggested approach for converting your I2C driver over to driver
26 - #ifdef out all your own I2C driver code (#ifndef CONFIG_DM_I2C)
30 no I2C driver
/external/u-boot/board/freescale/m53017evb/
DREADME36 - include/asm-m68k/fsl_i2c.h I2C structure and definition
93 CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
94 CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
95 CONFIG_SYS_I2C_SPEED -- define for I2C speed
96 CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
97 CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
150 I2C: ready
/external/u-boot/arch/arm/mach-rockchip/rk3288/
DKconfig40 provide access to display pins, I2C, SPI, UART and GPIOs.
49 provide access to display pins, I2C, SPI, UART and GPIOs.
58 provide access to display pins, I2C, SPI, UART and GPIOs.
67 I2C, SPI, UART, GPIOs and fan control.
84 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART,
110 provide access to display pins, I2C, SPI, UART and GPIOs.
128 I2C, SPI, UART, GPIOs.
/external/u-boot/drivers/tpm/
DKconfig33 This driver supports an Atmel TPM device connected on the I2C bus.
39 bool "Enable support for Infineon SLB9635/45 TPMs on I2C"
42 This driver supports Infineon TPM devices connected on the I2C bus.
48 bool "Enable I2C burst length limitation"
82 bool "STMicroelectronics ST33ZP24 I2C TPM"
85 This driver supports STMicroelectronics TPM devices connected on the I2C bus.
/external/u-boot/board/freescale/m52277evb/
DREADME36 - include/asm-m68k/fsl_i2c.h I2C structure and definition
84 CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
85 CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
86 CONFIG_SYS_I2C_SPEED -- define for I2C speed
87 CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
88 CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
146 I2C: ready
204 i2c - I2C sub-system
/external/u-boot/arch/arm/mach-rockchip/
DKconfig14 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
23 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
45 UART, SPI, I2C and PWMs.
58 USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
73 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
93 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
115 I2S, UARTs, SPI, I2C and PWMs.
150 USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
/external/u-boot/drivers/power/pmic/
DKconfig40 functions. It uses an I2C interface and is designed for use with
47 real-time clock, GPIOs, ADC and a few other features. It uses an I2C
116 accessed via an I2C interface. The device is used with Rockchip SoCs.
129 - I2C Configuration Interface
140 - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission
146 - I2C chip address: 0x40
210 via an I2C interface.
225 It is accessed via an I2C interface. The device is used with STM32MP1
/external/u-boot/arch/arm/dts/
Dmeson-gxl-s905x-khadas-vim.dts155 "I2C A SDA", "I2C A SCK", "I2C B SDA", "I2C B SCK",
/external/u-boot/board/freescale/m547xevb/
DREADME42 - include/asm-m68k/fsl_i2c.h I2C structure and definition
100 CONFIG_SYS_I2C_FSL -- define to use FSL common I2C driver
101 CONFIG_SYS_I2C_SOFT -- define for I2C bit-banged
102 CONFIG_SYS_I2C_SPEED -- define for I2C speed
103 CONFIG_SYS_I2C_SLAVE -- define for I2C slave address
104 CONFIG_SYS_I2C_OFFSET -- define for I2C base address offset
169 I2C: ready
234 i2c - I2C sub-system
/external/u-boot/arch/arm/mach-sti/
DKconfig24 - High speed connector (SD/I2C/USB interfaces)
25 - Low speed connector (UART/I2C/GPIO/SPI/PCM interfaces)
/external/u-boot/drivers/sound/
DKconfig25 bool "Enable I2C support for Samsung SoCs"
39 audio data and I2C for codec control. At present it only works
56 audio data and I2C for codec control. At present it only works
/external/u-boot/doc/device-tree-bindings/firmware/
Dnvidia,tegra186-bpmp.txt42 For example, it can provide access to certain I2C controllers, and the I2C
43 bindings represent each I2C controller as a device tree node. Such nodes should
54 services. Put another way, the numbering scheme for I2C buses is distinct from

123456