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/external/webp/src/dsp/
Dmips_macro.h42 I0, I1, I2, I3, I4, I5, I6, I7, I8, I9) \ argument
45 "ulw %[" #O2 "], " #I3 "+" XSTR(I9) "*" #I7 "(%[" #I0 "]) \n\t" \
53 I0, I1, I2, I3, I4, I5, I6, I7) \ argument
73 "subu %[" #IO3 "], %[" #IO3 "], %[" #I7 "] \n\t"
98 I0, I1, I2, I3, I4, I5, I6, I7) \ argument
105 "addq.ph %[" #O6 "], %[" #I3 "], %[" #I7 "] \n\t" \
106 "subq.ph %[" #O7 "], %[" #I3 "], %[" #I7 "] \n\t" \
161 I0, I1, I2, I3, I4, I5, I6, I7, \ argument
170 "addq.ph %[" #IO7 "], %[" #IO7 "], %[" #I7 "] \n\t" \
Denc_mips_dsp_r2.c29 I0, I1, I2, I3, I4, I5, I6, I7) \ argument
36 "addq.ph %[" #O6 "], %[" #I6 "], %[" #I7 "] \n\t" \
37 "subq.ph %[" #O7 "], %[" #I6 "], %[" #I7 "] \n\t"
56 #define MUL_HALF(O0, I0, I1, I2, I3, I4, I5, I6, I7, \ argument
63 "dpa.w.ph $ac0, %[" #I12 "], %[" #I7 "] \n\t" \
/external/llvm/test/CodeGen/Mips/
Dcmov.ll275 ; 32-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7
279 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
281 ; 32-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7
286 ; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I7]], $[[R0]]
290 ; 64-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7
294 ; 64-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
296 ; 64-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7
301 ; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I7]], $[[R0]]
579 ; 32-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7
583 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dcmov.ll275 ; 32-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7
279 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
281 ; 32-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7
286 ; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I7]], $[[R0]]
290 ; 64-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7
294 ; 64-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
296 ; 64-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7
301 ; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I7]], $[[R0]]
584 ; 32-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7
588 ; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]]
[all …]
/external/llvm/lib/Target/Sparc/
DSparcFrameLowering.cpp171 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue()
291 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) in verifyLeafProcRegUse()
317 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { in remapRegsForLeafProc()
344 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { in remapRegsForLeafProc()
DDelaySlotFiller.cpp387 if (reg < SP::I0 || reg > SP::I7) in combineRestoreADD()
415 if (reg < SP::I0 || reg > SP::I7) in combineRestoreOR()
453 if (reg < SP::I0 || reg > SP::I7) in combineRestoreSETHIi()
DSparcRegisterInfo.td159 def I7 : Ri<31, "I7">, DwarfRegNum<[31]>;
300 def I6_I7 : Rdi<30, "I6", [I6, I7]>;
DSparcRegisterInfo.cpp73 Reserved.set(SP::I7); in getReservedRegs()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcFrameLowering.cpp171 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue()
309 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) in verifyLeafProcRegUse()
335 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { in remapRegsForLeafProc()
361 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) { in remapRegsForLeafProc()
DDelaySlotFiller.cpp385 if (reg < SP::I0 || reg > SP::I7) in combineRestoreADD()
413 if (reg < SP::I0 || reg > SP::I7) in combineRestoreOR()
451 if (reg < SP::I0 || reg > SP::I7) in combineRestoreSETHIi()
DSparcRegisterInfo.td159 def I7 : Ri<31, "I7">, DwarfRegNum<[31]>;
300 def I6_I7 : Rdi<30, "I6", [I6, I7]>;
DSparcRegisterInfo.cpp73 Reserved.set(SP::I7); in getReservedRegs()
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcRegisterInfo.cpp33 : SparcGenRegisterInfo(SP::I7), Subtarget(st), TII(tii) { in SparcRegisterInfo()
51 Reserved.set(SP::I7); in getReservedRegs()
DSparcRegisterInfo.td83 def I7 : Ri<31, "I7">, DwarfRegNum<[31]>;
152 I7, // return address
DSparcISelLowering.cpp550 if (Reg >= SP::I0 && Reg <= SP::I7) in LowerCall()
576 if (Reg >= SP::I0 && Reg <= SP::I7) in LowerCall()
603 if (Reg >= SP::I0 && Reg <= SP::I7) in LowerCall()
1118 unsigned RetReg = SP::I7; in LowerRETURNADDR()
/external/clang/test/CodeGenObjC/
Dinterface-layout-64.m85 @interface I7 { interface
89 @interface I8 : I7 {
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/MCTargetDesc/
DSparcMCTargetDesc.cpp41 InitSparcMCRegisterInfo(X, SP::I7); in createSparcMCRegisterInfo()
/external/clang/test/ASTMerge/Inputs/
Dinterface2.m37 @interface I7 interface
Dinterface1.m38 @interface I7 interface
/external/ImageMagick/PerlMagick/t/reference/write/filter/
DEqualize.miff92 …}������ڭ��Lgb2�I{�͑��������������U��>ī P)W@b&_r-�}1��4��7�r3�u7��2x}/Y%,I7'@P'@b&7W'Ih(g}3}r9x7…
117 �Q�I7�_h�Yu�Qy�@r呥ٯĵ���Qu�I\�@h�0y�@��0��7��ru�Y%�Y
118 …��=��D��K��M��f��q��j��F��>��F��R��g��^���������Q.�%%�7I�7?�0�I�Q.�_%�)�I7�_h�����}�m}�_��0y�Yy…
119 …�a��^��\��\��\��Y��K��6�r(�h(�y,��<���������Q.�7�@�Q�Q�I�YI�0��I��@�Yn�x��m��0W�Qn�I7�m�}%�_
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.cpp72 case SP::I7: O << "\tret"; return true; in printSparcAliasInstr()
/external/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.cpp72 case SP::I7: O << "\tret"; return true; in printSparcAliasInstr()
/external/google-breakpad/src/common/
Dtest_assembler_unittest.cc750 #define I7(a,b,c,d,e,f,g) { a,b,c,d,e,f,g } macro
854 ASSERT_BYTES(contents, I7(0xe6, 0x43, 0xb8, 0xf1, 0xc9, 0x45, 0x14)); in TEST_F()
902 ASSERT_BYTES(contents, I7(0xf5, 0x0a, 0x72, 0x4f, 0x0b, 0x0d, 0x20)); in TEST_F()
964 ASSERT_BYTES(contents, I7(0xe6, 0x43, 0xb8, 0xf1, 0xc9, 0x45, 0x14)); in TEST_F()
1028 ASSERT_BYTES(contents, I7(0xf5, 0x0a, 0x72, 0x4f, 0x0b, 0x0d, 0x20)); in TEST_F()
/external/python/cpython2/Doc/library/
Dcookie.rst299 Set-Cookie: number="I7\012."
309 Set-Cookie: number="I7\012."
/external/u-boot/arch/arm/dts/
Dsun6i-a31-i7.dts51 model = "Mele I7 Quad top set box";

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