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Searched refs:I915_TILING_NONE (Results 1 – 20 of 20) sorted by relevance

/external/mesa3d/src/intel/isl/
Disl_drm.c38 return I915_TILING_NONE; in isl_tiling_to_i915_tiling()
51 return I915_TILING_NONE; in isl_tiling_to_i915_tiling()
61 case I915_TILING_NONE: in isl_tiling_from_i915_tiling()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_blit.c240 if (dst_tiling != I915_TILING_NONE) { in intelEmitCopyBlit()
244 if (src_tiling != I915_TILING_NONE) { in intelEmitCopyBlit()
531 if (dst_tiling != I915_TILING_NONE) { in intelEmitImmediateColorExpandBlit()
561 if (dst_tiling != I915_TILING_NONE) in intelEmitImmediateColorExpandBlit()
611 pitch, src_bo, src_offset, I915_TILING_NONE, in intel_emit_linear_blit()
612 pitch, dst_bo, dst_offset, I915_TILING_NONE, in intel_emit_linear_blit()
627 pitch, src_bo, src_offset, I915_TILING_NONE, in intel_emit_linear_blit()
628 pitch, dst_bo, dst_offset, I915_TILING_NONE, in intel_emit_linear_blit()
Dintel_mipmap_tree.c137 return I915_TILING_NONE; in intel_miptree_choose_tiling()
144 return I915_TILING_NONE; in intel_miptree_choose_tiling()
149 return I915_TILING_NONE; in intel_miptree_choose_tiling()
243 if (tiling != I915_TILING_NONE) in intel_miptree_create_for_bo()
676 if (mt->region->tiling != I915_TILING_NONE) in intel_miptree_map_raw()
874 if (mt->region->tiling != I915_TILING_NONE && in intel_miptree_map()
Dintel_regions.c295 case I915_TILING_NONE: in intel_region_get_tile_masks()
325 case I915_TILING_NONE: in intel_region_get_aligned_offset()
Dintel_pixel_read.c137 dst_stride, I915_TILING_NONE); in do_blit_readpixels()
Di830_texstate.c167 if (intelObj->mt->region->tiling != I915_TILING_NONE) { in i830_update_tex_unit()
Di915_vtbl.c530 if (region->tiling != I915_TILING_NONE) { in i915_set_buf_info_for_region()
617 depth_region->tiling != I915_TILING_NONE) in i915_set_draw_region()
Dintel_tex_image.c157 src_stride, I915_TILING_NONE); in try_pbo_upload()
Di915_texstate.c182 if (intelObj->mt->region->tiling != I915_TILING_NONE) { in i915_update_tex_unit()
Dintel_screen.c450 tiling = I915_TILING_NONE; in intel_create_image()
454 tiling = I915_TILING_NONE; in intel_create_image()
/external/minigbm/
Di915.c126 metadata.tiling = I915_TILING_NONE; in i915_add_combinations()
215 case I915_TILING_NONE: in i915_align_dimensions()
320 if (bo->tiling != I915_TILING_NONE) in i915_bo_from_format()
348 bo->tiling = I915_TILING_NONE; in i915_bo_create_for_modifier()
468 if (bo->tiling == I915_TILING_NONE) { in i915_bo_map()
518 if (bo->tiling == I915_TILING_NONE) { in i915_bo_invalidate()
540 if (!i915->has_llc && bo->tiling == I915_TILING_NONE) in i915_bo_flush()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_bufmgr.c151 if (tiling == I915_TILING_NONE) in bo_tile_size()
171 if (tiling == I915_TILING_NONE) in bo_tile_pitch()
386 bo->tiling_mode = I915_TILING_NONE; in bo_alloc_internal()
431 return bo_alloc_internal(bufmgr, name, size, 0, I915_TILING_NONE, 0, 0); in brw_bo_alloc()
477 if (tiling == I915_TILING_NONE) in brw_bo_alloc_tiled_2d()
931 if (bo->tiling_mode != I915_TILING_NONE && !(flags & MAP_RAW)) in brw_bo_map()
1193 assert(tiling_mode == I915_TILING_NONE || in brw_bo_gem_create_from_prime_tiled()
Dintel_screen.c354 [I915_TILING_NONE] = DRM_FORMAT_MOD_LINEAR, in tiling_to_modifier()
370 if (tiling != I915_TILING_NONE && (image->offset & 0xfff)) { in intel_image_warn_if_unaligned()
/external/libdrm/intel/
Dintel_bufmgr.c245 *tiling_mode = I915_TILING_NONE; in drm_intel_bo_set_tiling()
256 *tiling_mode = I915_TILING_NONE; in drm_intel_bo_get_tiling()
Dintel_bufmgr_gem.c320 if (*tiling_mode == I915_TILING_NONE) in drm_intel_gem_bo_tile_size()
337 *tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_tile_size()
366 if (*tiling_mode == I915_TILING_NONE) in drm_intel_gem_bo_tile_pitch()
384 *tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_tile_pitch()
587 if (bufmgr_gem->gen < 4 && bo_gem->tiling_mode != I915_TILING_NONE) { in drm_intel_bo_gem_set_in_aperture_size()
821 bo_gem->tiling_mode = I915_TILING_NONE; in drm_intel_gem_bo_alloc_internal()
862 I915_TILING_NONE, 0, in drm_intel_gem_bo_alloc_for_render()
873 I915_TILING_NONE, 0, 0); in drm_intel_gem_bo_alloc()
904 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE) in drm_intel_gem_bo_alloc_tiled()
921 if (tiling == I915_TILING_NONE) in drm_intel_gem_bo_alloc_tiled()
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Dintel_bufmgr_fake.c848 *tiling_mode = I915_TILING_NONE; in drm_intel_fake_bo_alloc_tiled()
/external/mesa3d/src/intel/vulkan/
Danv_android.c139 case I915_TILING_NONE: in anv_image_from_gralloc()
/external/mesa3d/include/drm-uapi/
Di915_drm.h1127 #define I915_TILING_NONE 0 macro
/external/libdrm/include/drm/
Di915_drm.h1169 #define I915_TILING_NONE 0 macro
/external/kernel-headers/original/uapi/drm/
Di915_drm.h1199 #define I915_TILING_NONE 0 macro