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Searched refs:I915_TILING_Y (Results 1 – 18 of 18) sorted by relevance

/external/mesa3d/src/intel/isl/
Disl_drm.c44 return I915_TILING_Y; in isl_tiling_to_i915_tiling()
67 case I915_TILING_Y: in isl_tiling_from_i915_tiling()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_clear.c137 if (stencilRegion->tiling == I915_TILING_Y || in intelClear()
157 if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL) in intelClear()
Dintel_blit.c236 bool dst_y_tiled = dst_tiling == I915_TILING_Y; in intelEmitCopyBlit()
237 bool src_y_tiled = src_tiling == I915_TILING_Y; in intelEmitCopyBlit()
441 assert(region->tiling != I915_TILING_Y); in intelClearWithBlit()
534 if (dst_tiling == I915_TILING_Y) in intelEmitImmediateColorExpandBlit()
Dintel_regions.c302 case I915_TILING_Y: in intel_region_get_tile_masks()
331 case I915_TILING_Y: in intel_region_get_aligned_offset()
Dintel_tex_subimage.c64 if (intelImage->mt->region->tiling == I915_TILING_Y) in intel_blit_texsubimage()
Dintel_mipmap_tree.c135 return I915_TILING_Y; in intel_miptree_choose_tiling()
188 bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X); in intel_miptree_create()
191 y_or_x ? I915_TILING_Y : tiling, in intel_miptree_create()
Di830_texstate.c169 if (intelObj->mt->region->tiling == I915_TILING_Y) in i830_update_tex_unit()
Di915_texstate.c184 if (intelObj->mt->region->tiling == I915_TILING_Y) in i915_update_tex_unit()
Di915_vtbl.c532 if (region->tiling == I915_TILING_Y) in i915_set_buf_info_for_region()
/external/minigbm/
Di915.c174 metadata.tiling = I915_TILING_Y; in i915_add_combinations()
232 case I915_TILING_Y: in i915_align_dimensions()
354 bo->tiling = I915_TILING_Y; in i915_bo_create_for_modifier()
/external/mesa3d/include/drm-uapi/
Di915_drm.h1129 #define I915_TILING_Y 2 macro
1130 #define I915_TILING_LAST I915_TILING_Y
/external/mesa3d/src/intel/vulkan/
Danv_android.c145 case I915_TILING_Y: in anv_image_from_gralloc()
/external/libdrm/include/drm/
Di915_drm.h1171 #define I915_TILING_Y 2 macro
1172 #define I915_TILING_LAST I915_TILING_Y
/external/kernel-headers/original/uapi/drm/
Di915_drm.h1201 #define I915_TILING_Y 2 macro
1202 #define I915_TILING_LAST I915_TILING_Y
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_bufmgr.c467 else if (tiling == I915_TILING_Y) in brw_bo_alloc_tiled_2d()
1195 tiling_mode == I915_TILING_Y); in brw_bo_gem_create_from_prime_tiled()
Dintel_screen.c356 [I915_TILING_Y] = I915_FORMAT_MOD_Y_TILED, in tiling_to_modifier()
Dintel_mipmap_tree.c1687 I915_TILING_Y, buf->pitch, alloc_flags); in intel_alloc_aux_buffer()
/external/libdrm/intel/
Dintel_bufmgr_gem.c371 && *tiling_mode == I915_TILING_Y)) in drm_intel_gem_bo_tile_pitch()
908 && tiling == I915_TILING_Y)) in drm_intel_gem_bo_alloc_tiled()
910 else if (tiling == I915_TILING_Y) in drm_intel_gem_bo_alloc_tiled()