Searched refs:ICC_IGRPEN0_EL1 (Results 1 – 6 of 6) sorted by relevance
| /external/u-boot/arch/arm/include/asm/ |
| D | gic.h | 102 #define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 macro
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | gicv3-regs.txt | 37 # CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}
145 # CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | gicv3-regs.txt | 37 # CHECK: mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}
145 # CHECK: msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenSystemOperands.inc | 698 ICC_IGRPEN0_EL1 = 50790,
2525 { "ICC_IGRPEN0_EL1", 0xC666, true, true, {} }, // 543
2981 { "ICC_IGRPEN0_EL1", 543 },
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 893 def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 1063 def : RWSysReg<"ICC_IGRPEN0_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b110>;
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