• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2009
4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5  */
6 
7 #ifndef __DW_I2C_H_
8 #define __DW_I2C_H_
9 
10 struct i2c_regs {
11 	u32 ic_con;		/* 0x00 */
12 	u32 ic_tar;		/* 0x04 */
13 	u32 ic_sar;		/* 0x08 */
14 	u32 ic_hs_maddr;	/* 0x0c */
15 	u32 ic_cmd_data;	/* 0x10 */
16 	u32 ic_ss_scl_hcnt;	/* 0x14 */
17 	u32 ic_ss_scl_lcnt;	/* 0x18 */
18 	u32 ic_fs_scl_hcnt;	/* 0x1c */
19 	u32 ic_fs_scl_lcnt;	/* 0x20 */
20 	u32 ic_hs_scl_hcnt;	/* 0x24 */
21 	u32 ic_hs_scl_lcnt;	/* 0x28 */
22 	u32 ic_intr_stat;	/* 0x2c */
23 	u32 ic_intr_mask;	/* 0x30 */
24 	u32 ic_raw_intr_stat;	/* 0x34 */
25 	u32 ic_rx_tl;		/* 0x38 */
26 	u32 ic_tx_tl;		/* 0x3c */
27 	u32 ic_clr_intr;	/* 0x40 */
28 	u32 ic_clr_rx_under;	/* 0x44 */
29 	u32 ic_clr_rx_over;	/* 0x48 */
30 	u32 ic_clr_tx_over;	/* 0x4c */
31 	u32 ic_clr_rd_req;	/* 0x50 */
32 	u32 ic_clr_tx_abrt;	/* 0x54 */
33 	u32 ic_clr_rx_done;	/* 0x58 */
34 	u32 ic_clr_activity;	/* 0x5c */
35 	u32 ic_clr_stop_det;	/* 0x60 */
36 	u32 ic_clr_start_det;	/* 0x64 */
37 	u32 ic_clr_gen_call;	/* 0x68 */
38 	u32 ic_enable;		/* 0x6c */
39 	u32 ic_status;		/* 0x70 */
40 	u32 ic_txflr;		/* 0x74 */
41 	u32 ic_rxflr;		/* 0x78 */
42 	u32 ic_sda_hold;	/* 0x7c */
43 	u32 ic_tx_abrt_source;	/* 0x80 */
44 	u8 res1[0x18];		/* 0x84 */
45 	u32 ic_enable_status;	/* 0x9c */
46 };
47 
48 #if !defined(IC_CLK)
49 #define IC_CLK			166
50 #endif
51 #define NANO_TO_MICRO		1000
52 
53 /* High and low times in different speed modes (in ns) */
54 #define MIN_SS_SCL_HIGHTIME	4000
55 #define MIN_SS_SCL_LOWTIME	4700
56 #define MIN_FS_SCL_HIGHTIME	600
57 #define MIN_FS_SCL_LOWTIME	1300
58 #define MIN_HS_SCL_HIGHTIME	60
59 #define MIN_HS_SCL_LOWTIME	160
60 
61 /* Worst case timeout for 1 byte is kept as 2ms */
62 #define I2C_BYTE_TO		(CONFIG_SYS_HZ/500)
63 #define I2C_STOPDET_TO		(CONFIG_SYS_HZ/500)
64 #define I2C_BYTE_TO_BB		(I2C_BYTE_TO * 16)
65 
66 /* i2c control register definitions */
67 #define IC_CON_SD		0x0040
68 #define IC_CON_RE		0x0020
69 #define IC_CON_10BITADDRMASTER	0x0010
70 #define IC_CON_10BITADDR_SLAVE	0x0008
71 #define IC_CON_SPD_MSK		0x0006
72 #define IC_CON_SPD_SS		0x0002
73 #define IC_CON_SPD_FS		0x0004
74 #define IC_CON_SPD_HS		0x0006
75 #define IC_CON_MM		0x0001
76 
77 /* i2c target address register definitions */
78 #define TAR_ADDR		0x0050
79 
80 /* i2c slave address register definitions */
81 #define IC_SLAVE_ADDR		0x0002
82 
83 /* i2c data buffer and command register definitions */
84 #define IC_CMD			0x0100
85 #define IC_STOP			0x0200
86 
87 /* i2c interrupt status register definitions */
88 #define IC_GEN_CALL		0x0800
89 #define IC_START_DET		0x0400
90 #define IC_STOP_DET		0x0200
91 #define IC_ACTIVITY		0x0100
92 #define IC_RX_DONE		0x0080
93 #define IC_TX_ABRT		0x0040
94 #define IC_RD_REQ		0x0020
95 #define IC_TX_EMPTY		0x0010
96 #define IC_TX_OVER		0x0008
97 #define IC_RX_FULL		0x0004
98 #define IC_RX_OVER 		0x0002
99 #define IC_RX_UNDER		0x0001
100 
101 /* fifo threshold register definitions */
102 #define IC_TL0			0x00
103 #define IC_TL1			0x01
104 #define IC_TL2			0x02
105 #define IC_TL3			0x03
106 #define IC_TL4			0x04
107 #define IC_TL5			0x05
108 #define IC_TL6			0x06
109 #define IC_TL7			0x07
110 #define IC_RX_TL		IC_TL0
111 #define IC_TX_TL		IC_TL0
112 
113 /* i2c enable register definitions */
114 #define IC_ENABLE_0B		0x0001
115 
116 /* i2c status register  definitions */
117 #define IC_STATUS_SA		0x0040
118 #define IC_STATUS_MA		0x0020
119 #define IC_STATUS_RFF		0x0010
120 #define IC_STATUS_RFNE		0x0008
121 #define IC_STATUS_TFE		0x0004
122 #define IC_STATUS_TFNF		0x0002
123 #define IC_STATUS_ACT		0x0001
124 
125 /* Speed Selection */
126 #define IC_SPEED_MODE_STANDARD	1
127 #define IC_SPEED_MODE_FAST	2
128 #define IC_SPEED_MODE_MAX	3
129 
130 #define I2C_MAX_SPEED		3400000
131 #define I2C_FAST_SPEED		400000
132 #define I2C_STANDARD_SPEED	100000
133 
134 #endif /* __DW_I2C_H_ */
135