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Searched refs:IDIS (Results 1 – 25 of 26) sorted by relevance

12

/external/u-boot/board/quipos/cairo/
Dcairo.h36 MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
39 MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
40 MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
50 MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
51 MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
52 MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
53 MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
54 MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
56 MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \
57 MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \
[all …]
/external/u-boot/board/overo/
Dovero.h40 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
41 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
42 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
50 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
51 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
52 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
53 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
54 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
55 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
56 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
[all …]
Dcommon.c81 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
82 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
83 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
84 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
85 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
86 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
87 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
88 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
89 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
90 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/amazon/kc1/
Dkc1.h33 { CAM_SHUTTER, (IDIS | DIS | M7) }, /* safe_mode */
34 { CAM_STROBE, (IDIS | DIS | M7) }, /* safe_mode */
35 { CAM_GLOBALRESET, (IDIS | DIS | M7) }, /* safe_mode */
37 { HDQ_SIO, (IDIS | DIS | M7) }, /* safe_mode */
51 { MCSPI1_CLK, (IDIS | DIS | M7) }, /* safe_mode */
52 { MCSPI1_SOMI, (IDIS | DIS | M7) }, /* safe_mode */
53 { MCSPI1_SIMO, (IDIS | DIS | M7) }, /* safe_mode */
54 { MCSPI1_CS0, (IDIS | DIS | M7) }, /* safe_mode */
55 { MCSPI1_CS1, (IDIS | DIS | M7) }, /* safe_mode */
56 { MCSPI1_CS2, (IDIS | DIS | M7) }, /* safe_mode */
[all …]
/external/u-boot/board/compulab/cm_t3517/
Dmux.c53 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
54 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); in set_muxconf_regs()
57 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
58 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
59 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
60 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
61 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
62 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
63 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
64 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
[all …]
/external/u-boot/board/timll/devkit8000/
Ddevkit8000.h72 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
73 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
74 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
75 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
76 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
77 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
78 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
79 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
80 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
81 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/compulab/cm_t35/
Dcm_t35.c165 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ in cm_t3x_set_common_muxconf()
166 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/ in cm_t3x_set_common_muxconf()
169 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in cm_t3x_set_common_muxconf()
170 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in cm_t3x_set_common_muxconf()
171 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in cm_t3x_set_common_muxconf()
172 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in cm_t3x_set_common_muxconf()
173 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in cm_t3x_set_common_muxconf()
174 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in cm_t3x_set_common_muxconf()
175 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in cm_t3x_set_common_muxconf()
176 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in cm_t3x_set_common_muxconf()
[all …]
/external/u-boot/board/corscience/tricorder/
Dtricorder.h69 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
70 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
71 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
72 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
73 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
74 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
75 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
76 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\
78 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\
[all …]
/external/u-boot/board/ti/beagle/
Dbeagle.h78 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
79 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
80 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
81 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
82 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
83 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
84 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
85 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
86 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
87 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/nokia/rx51/
Drx51.h74 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
75 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
76 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
77 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
78 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
79 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
80 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
81 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
82 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
83 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/pandora/
Dpandora.h65 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
66 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
67 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
68 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
69 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
70 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
71 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
72 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
73 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
74 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/ti/evm/
Devm.h88 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
89 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
90 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
91 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
92 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
93 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
94 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
95 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
96 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
97 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/technexion/twister/
Dtwister.h91 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
92 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
93 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
94 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
95 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
96 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
97 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
98 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
99 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
100 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/technexion/tao3530/
Dtao3530.h69 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
70 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
71 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
72 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
73 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
74 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
75 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
76 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
78 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/logicpd/am3517evm/
Dam3517evm.h82 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
87 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
89 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
90 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
91 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/lg/sniper/
Dsniper.h53 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \
55 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \
56 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\
58 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\
78 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTD | DIS | M7)) \
79 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTD | DIS | M4)) /* gpio_52 */ \
81 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* gpio_54 */ \
82 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTD | DIS | M4)) /* gpio_55 */ \
83 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M3)) /* gpio_56 */ \
84 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | DIS | M4)) /* gpio_57 */ \
[all …]
/external/u-boot/board/isee/igep00x0/
Digep00x0.h57 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
58 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
59 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
60 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
61 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
62 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
63 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
64 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
65 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
66 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
[all …]
/external/u-boot/board/teejet/mt_ventoux/
Dmt_ventoux.h87 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
89 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
90 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
91 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
92 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
93 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
94 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
95 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
96 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/8dtech/eco5pk/
Deco5pk.h79 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
80 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
81 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
82 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
83 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
84 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
85 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
86 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
87 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/logicpd/zoom1/
Dzoom1.h76 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
77 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
78 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
79 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
80 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
81 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
82 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
83 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
84 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
85 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/ti/am3517crane/
Dam3517crane.h83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
108 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))\
109 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\
116 MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0))/*TP*/\
117 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))\
118 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))\
[all …]
/external/u-boot/board/htkw/mcx/
Dmcx.h104 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
115 MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
116 MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
117 MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
118 MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
121 MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
129 MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
130 MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
131 MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
132 MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
[all …]
/external/u-boot/board/logicpd/omap3som/
Domap3logic.h85 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ in set_muxconf_regs()
86 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/ in set_muxconf_regs()
88 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in set_muxconf_regs()
89 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in set_muxconf_regs()
90 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in set_muxconf_regs()
91 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in set_muxconf_regs()
92 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in set_muxconf_regs()
93 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in set_muxconf_regs()
94 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in set_muxconf_regs()
95 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in set_muxconf_regs()
[all …]
/external/u-boot/arch/arm/include/asm/arch-omap5/
Dmux_omap5.h33 #define IDIS (0 << 8) macro
/external/u-boot/arch/arm/include/asm/arch-omap4/
Dmux_omap4.h41 #define IDIS (0 << 8) macro

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