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Searched refs:IMX_DMAC_BASE (Results 1 – 1 of 1) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-imx/
Dimx-regs.h37 #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) macro
334 #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
335 #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
336 #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
337 #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
338 #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
339 #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
340 #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
341 #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
342 #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
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