Searched refs:IOMUXC_BASE (Results 1 – 2 of 2) sorted by relevance
660 #define IOMUXC_BASE 0x43FAC000 macro661 #define IOMUXC_SW_MUX_CTL(x) (IOMUXC_BASE + 0xc + (x) * 4)662 #define IOMUXC_SW_PAD_CTL(x) (IOMUXC_BASE + 0x154 + (x) * 4)825 #define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C)826 #define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270)827 #define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274)828 #define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278)829 #define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C)830 #define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280)831 #define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284)[all …]
107 reg = IOMUXC_BASE + (mode & 0x1fc); in mx31_gpio_mux()121 reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4; in mx31_set_pad()134 struct iomuxc_regs *iomuxc = (struct iomuxc_regs *)IOMUXC_BASE; in mx31_set_gpr()