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Searched refs:IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (Results 1 – 12 of 12) sorted by relevance

/external/u-boot/board/engicam/imx6q/
Dimx6q.c183 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) | in setup_display()
/external/u-boot/board/aristainetos/
Daristainetos-v2.c468 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) in enable_lvds()
560 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) in enable_spi_display()
/external/u-boot/board/kosagi/novena/
Dvideo.c423 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display_clock()
/external/u-boot/board/ge/bx50v3/
Dbx50v3.c491 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display_b850v3()
532 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK, in setup_display_bx50v3()
/external/u-boot/board/embest/mx6boards/
Dmx6boards.c495 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display()
/external/u-boot/board/advantech/dms-ba16/
Ddms-ba16.c428 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display()
/external/u-boot/board/freescale/mx6sabreauto/
Dmx6sabreauto.c553 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK | in setup_display()
/external/u-boot/board/toradex/colibri_imx6/
Dcolibri_imx6.c612 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK in setup_display()
/external/u-boot/board/boundary/nitrogen6x/
Dnitrogen6x.c796 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK in setup_display()
/external/u-boot/board/toradex/apalis_imx6/
Dapalis_imx6.c734 reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK in setup_display()
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dimx-regs.h566 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) macro
/external/u-boot/board/gateworks/gw_ventana/
Dgw_ventana.c472 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) in setup_display()