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Searched refs:IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET (Results 1 – 12 of 12) sorted by relevance

/external/u-boot/board/engicam/imx6q/
Dimx6q.c185 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); in setup_display()
/external/u-boot/board/aristainetos/
Daristainetos-v2.c470 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); in enable_lvds()
562 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); in enable_spi_display()
/external/u-boot/board/kosagi/novena/
Dvideo.c426 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | in setup_display_clock()
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dimx-regs.h565 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6 macro
566 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
/external/u-boot/board/embest/mx6boards/
Dmx6boards.c498 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); in setup_display()
/external/u-boot/board/advantech/dms-ba16/
Ddms-ba16.c432 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); in setup_display()
/external/u-boot/board/ge/bx50v3/
Dbx50v3.c534 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)); in setup_display_bx50v3()
/external/u-boot/board/freescale/mx6sabreauto/
Dmx6sabreauto.c556 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) | in setup_display()
/external/u-boot/board/toradex/colibri_imx6/
Dcolibri_imx6.c615 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); in setup_display()
/external/u-boot/board/boundary/nitrogen6x/
Dnitrogen6x.c799 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); in setup_display()
/external/u-boot/board/toradex/apalis_imx6/
Dapalis_imx6.c737 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); in setup_display()
/external/u-boot/board/gateworks/gw_ventana/
Dgw_ventana.c474 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); in setup_display()