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Searched refs:IP3_27_24 (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/drivers/pinctrl/renesas/
Dpfc-r8a77970.c98 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
183 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, … macro
265 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
512 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
513 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
514 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
2291 IP3_27_24
Dpfc-r8a77995.c56 #define GPSR1_23 F_(DU_DR7, IP3_27_24)
231 #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,… macro
357 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
644 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
645 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
646 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
2293 IP3_27_24
Dpfc-r8a77990.c78 #define GPSR1_7 F_(A7, IP3_27_24)
219 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D… macro
367 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
685 PINMUX_IPSR_GPSR(IP3_27_24, A7),
686 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
687 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
688 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
689 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
4963 IP3_27_24
Dpfc-r8a7795.c70 #define GPSR1_15 F_(A15, IP3_27_24)
244 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(… macro
409 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
798 PINMUX_IPSR_GPSR(IP3_27_24, A15),
799 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
800 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
801 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
802 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
803 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
5387 IP3_27_24
Dpfc-r8a7796.c76 #define GPSR1_15 F_(A15, IP3_27_24)
250 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(… macro
415 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
800 PINMUX_IPSR_GPSR(IP3_27_24, A15),
801 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
802 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
803 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
804 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
805 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
5331 IP3_27_24