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Searched refs:IR3_REG_SSA (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3.h91 IR3_REG_SSA = 0x4000, /* 'instr' is ptr to assigning instr */ enumerator
756 if (reg->flags & (IR3_REG_SSA | IR3_REG_ARRAY)) { in ssa()
1021 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = src; in ir3_MOV()
1035 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = src; in ir3_COV()
1065 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1078 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1079 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1093 ir3_reg_create(instr, 0, IR3_REG_SSA | aflags)->instr = a; \
1094 ir3_reg_create(instr, 0, IR3_REG_SSA | bflags)->instr = b; \
1095 ir3_reg_create(instr, 0, IR3_REG_SSA | cflags)->instr = c; \
[all …]
Dir3_group.c71 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = in; in arr_insert_mov_in()
212 ir3_reg_create(instr, 0, IR3_REG_SSA); /* dummy dst */ in pad_and_group_input()
Dir3_cp.c245 *dstflags &= ~IR3_REG_SSA; in combine_flags()
246 *dstflags |= srcflags & IR3_REG_SSA; in combine_flags()
Dir3_print.c124 } else if (reg->flags & IR3_REG_SSA) { in print_reg_name()
Dir3_compiler_nir.c370 ir3_reg_create(mov, 0, IR3_REG_SSA)->instr = src; in create_array_store()
628 ir3_reg_create(collect, 0, IR3_REG_SSA)->instr = arr[i]; in create_collect()
645 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV); in create_indirect_load()
758 ir3_reg_create(split, 0, IR3_REG_SSA); in split_dest()
759 ir3_reg_create(split, 0, IR3_REG_SSA)->instr = src; in split_dest()
2603 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = src; in resolve_phis()
3110 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.x */ in emit_instructions()
3111 ir3_reg_create(instr, 0, IR3_REG_SSA); /* r0.y */ in emit_instructions()
Dir3_ra.c1043 reg->flags &= ~(IR3_REG_SSA | IR3_REG_PHI_SRC); in reg_assign()
/external/mesa3d/src/gallium/docs/source/drivers/freedreno/
Dir3-notes.rst44 …s. And additionally, for normal (non-const, etc) src registers, the ``IR3_REG_SSA`` flag is set a…
113 If ``IR3_REG_SSA`` is set on a src register, the actual register