1 /* 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 */ 27 28 #ifndef _INTEL_CHIPSET_H 29 #define _INTEL_CHIPSET_H 30 31 #define PCI_CHIP_I810 0x7121 32 #define PCI_CHIP_I810_DC100 0x7123 33 #define PCI_CHIP_I810_E 0x7125 34 #define PCI_CHIP_I815 0x1132 35 36 #define PCI_CHIP_I830_M 0x3577 37 #define PCI_CHIP_845_G 0x2562 38 #define PCI_CHIP_I855_GM 0x3582 39 #define PCI_CHIP_I865_G 0x2572 40 41 #define PCI_CHIP_I915_G 0x2582 42 #define PCI_CHIP_E7221_G 0x258A 43 #define PCI_CHIP_I915_GM 0x2592 44 #define PCI_CHIP_I945_G 0x2772 45 #define PCI_CHIP_I945_GM 0x27A2 46 #define PCI_CHIP_I945_GME 0x27AE 47 48 #define PCI_CHIP_Q35_G 0x29B2 49 #define PCI_CHIP_G33_G 0x29C2 50 #define PCI_CHIP_Q33_G 0x29D2 51 52 #define PCI_CHIP_IGD_GM 0xA011 53 #define PCI_CHIP_IGD_G 0xA001 54 55 #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM) 56 #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) 57 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) 58 59 #define PCI_CHIP_I965_G 0x29A2 60 #define PCI_CHIP_I965_Q 0x2992 61 #define PCI_CHIP_I965_G_1 0x2982 62 #define PCI_CHIP_I946_GZ 0x2972 63 #define PCI_CHIP_I965_GM 0x2A02 64 #define PCI_CHIP_I965_GME 0x2A12 65 66 #define PCI_CHIP_GM45_GM 0x2A42 67 68 #define PCI_CHIP_IGD_E_G 0x2E02 69 #define PCI_CHIP_Q45_G 0x2E12 70 #define PCI_CHIP_G45_G 0x2E22 71 #define PCI_CHIP_G41_G 0x2E32 72 73 #define PCI_CHIP_ILD_G 0x0042 74 #define PCI_CHIP_ILM_G 0x0046 75 76 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ 77 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 78 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 79 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */ 80 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 81 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 82 #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ 83 84 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */ 85 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162 86 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ 87 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 88 #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ 89 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ 90 91 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ 92 #define PCI_CHIP_HASWELL_GT2 0x0412 93 #define PCI_CHIP_HASWELL_GT3 0x0422 94 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ 95 #define PCI_CHIP_HASWELL_M_GT2 0x0416 96 #define PCI_CHIP_HASWELL_M_GT3 0x0426 97 #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ 98 #define PCI_CHIP_HASWELL_S_GT2 0x041A 99 #define PCI_CHIP_HASWELL_S_GT3 0x042A 100 #define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ 101 #define PCI_CHIP_HASWELL_B_GT2 0x041B 102 #define PCI_CHIP_HASWELL_B_GT3 0x042B 103 #define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ 104 #define PCI_CHIP_HASWELL_E_GT2 0x041E 105 #define PCI_CHIP_HASWELL_E_GT3 0x042E 106 #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ 107 #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 108 #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 109 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ 110 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 111 #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 112 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ 113 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A 114 #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A 115 #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ 116 #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B 117 #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B 118 #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ 119 #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E 120 #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E 121 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ 122 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 123 #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 124 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ 125 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 126 #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 127 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ 128 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A 129 #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A 130 #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ 131 #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B 132 #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B 133 #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ 134 #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E 135 #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E 136 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ 137 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 138 #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 139 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ 140 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 141 #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 142 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ 143 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A 144 #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A 145 #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ 146 #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B 147 #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B 148 #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ 149 #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E 150 #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E 151 #define BDW_SPARE 0x2 152 #define BDW_ULT 0x6 153 #define BDW_SERVER 0xa 154 #define BDW_IRIS 0xb 155 #define BDW_WORKSTATION 0xd 156 #define BDW_ULX 0xe 157 158 #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ 159 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 160 #define PCI_CHIP_VALLEYVIEW_2 0x0f32 161 #define PCI_CHIP_VALLEYVIEW_3 0x0f33 162 163 #define PCI_CHIP_CHERRYVIEW_0 0x22b0 164 #define PCI_CHIP_CHERRYVIEW_1 0x22b1 165 #define PCI_CHIP_CHERRYVIEW_2 0x22b2 166 #define PCI_CHIP_CHERRYVIEW_3 0x22b3 167 168 #define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 169 #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 170 #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ 171 #define PCI_CHIP_SKYLAKE_H_GT1 0x190B 172 #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ 173 #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 174 #define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ 175 #define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */ 176 #define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 177 #define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */ 178 #define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */ 179 #define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B 180 #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D 181 #define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E 182 #define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */ 183 #define PCI_CHIP_SKYLAKE_ULT_GT3_0 0x1923 184 #define PCI_CHIP_SKYLAKE_ULT_GT3_1 0x1926 185 #define PCI_CHIP_SKYLAKE_ULT_GT3_2 0x1927 186 #define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A 187 #define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ 188 #define PCI_CHIP_SKYLAKE_SRV_GT3 0x192D 189 #define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 190 #define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A 191 #define PCI_CHIP_SKYLAKE_H_GT4 0x193B 192 #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D 193 194 #define PCI_CHIP_KABYLAKE_ULT_GT2 0x5916 195 #define PCI_CHIP_KABYLAKE_ULT_GT1_5 0x5913 196 #define PCI_CHIP_KABYLAKE_ULT_GT1 0x5906 197 #define PCI_CHIP_KABYLAKE_ULT_GT3_0 0x5923 198 #define PCI_CHIP_KABYLAKE_ULT_GT3_1 0x5926 199 #define PCI_CHIP_KABYLAKE_ULT_GT3_2 0x5927 200 #define PCI_CHIP_KABYLAKE_ULT_GT2F 0x5921 201 #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 202 #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E 203 #define PCI_CHIP_KABYLAKE_ULX_GT2 0x591E 204 #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 205 #define PCI_CHIP_KABYLAKE_M_GT2 0x5917 206 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 207 #define PCI_CHIP_KABYLAKE_HALO_GT2 0x591B 208 #define PCI_CHIP_KABYLAKE_HALO_GT4 0x593B 209 #define PCI_CHIP_KABYLAKE_HALO_GT1_0 0x5908 210 #define PCI_CHIP_KABYLAKE_HALO_GT1_1 0x590B 211 #define PCI_CHIP_KABYLAKE_SRV_GT2 0x591A 212 #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A 213 #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D 214 215 #define PCI_CHIP_BROXTON_0 0x0A84 216 #define PCI_CHIP_BROXTON_1 0x1A84 217 #define PCI_CHIP_BROXTON_2 0x5A84 218 #define PCI_CHIP_BROXTON_3 0x1A85 219 #define PCI_CHIP_BROXTON_4 0x5A85 220 221 #define PCI_CHIP_GLK 0x3184 222 #define PCI_CHIP_GLK_2X6 0x3185 223 224 #define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 225 #define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 226 #define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99 227 #define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 228 #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 229 #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 230 #define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A 231 #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B 232 #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 233 #define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1 234 #define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4 235 #define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0 236 #define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3 237 #define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9 238 #define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2 239 #define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5 240 #define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6 241 #define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 242 #define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 243 244 #define PCI_CHIP_CANNONLAKE_0 0x5A51 245 #define PCI_CHIP_CANNONLAKE_1 0x5A59 246 #define PCI_CHIP_CANNONLAKE_2 0x5A41 247 #define PCI_CHIP_CANNONLAKE_3 0x5A49 248 #define PCI_CHIP_CANNONLAKE_4 0x5A52 249 #define PCI_CHIP_CANNONLAKE_5 0x5A5A 250 #define PCI_CHIP_CANNONLAKE_6 0x5A42 251 #define PCI_CHIP_CANNONLAKE_7 0x5A4A 252 #define PCI_CHIP_CANNONLAKE_8 0x5A50 253 #define PCI_CHIP_CANNONLAKE_9 0x5A40 254 #define PCI_CHIP_CANNONLAKE_10 0x5A54 255 #define PCI_CHIP_CANNONLAKE_11 0x5A5C 256 #define PCI_CHIP_CANNONLAKE_12 0x5A44 257 #define PCI_CHIP_CANNONLAKE_13 0x5A4C 258 259 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ 260 (devid) == PCI_CHIP_I915_GM || \ 261 (devid) == PCI_CHIP_I945_GM || \ 262 (devid) == PCI_CHIP_I945_GME || \ 263 (devid) == PCI_CHIP_I965_GM || \ 264 (devid) == PCI_CHIP_I965_GME || \ 265 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \ 266 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ 267 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2) 268 269 #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ 270 (devid) == PCI_CHIP_Q45_G || \ 271 (devid) == PCI_CHIP_G45_G || \ 272 (devid) == PCI_CHIP_G41_G) 273 #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) 274 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) 275 276 #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) 277 #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) 278 279 #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ 280 (devid) == PCI_CHIP_E7221_G || \ 281 (devid) == PCI_CHIP_I915_GM) 282 283 #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \ 284 (devid) == PCI_CHIP_I945_GME) 285 286 #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \ 287 (devid) == PCI_CHIP_I945_GM || \ 288 (devid) == PCI_CHIP_I945_GME || \ 289 IS_G33(devid)) 290 291 #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \ 292 (devid) == PCI_CHIP_Q33_G || \ 293 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid)) 294 295 #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \ 296 (devid) == PCI_CHIP_845_G || \ 297 (devid) == PCI_CHIP_I855_GM || \ 298 (devid) == PCI_CHIP_I865_G) 299 300 #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid)) 301 302 #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \ 303 (devid) == PCI_CHIP_I965_Q || \ 304 (devid) == PCI_CHIP_I965_G_1 || \ 305 (devid) == PCI_CHIP_I965_GM || \ 306 (devid) == PCI_CHIP_I965_GME || \ 307 (devid) == PCI_CHIP_I946_GZ || \ 308 IS_G4X(devid)) 309 310 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) 311 312 #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \ 313 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \ 314 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ 315 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ 316 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ 317 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ 318 (devid) == PCI_CHIP_SANDYBRIDGE_S) 319 320 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ 321 IS_HASWELL(devid) || \ 322 IS_VALLEYVIEW(devid)) 323 324 #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ 325 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \ 326 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ 327 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \ 328 (devid) == PCI_CHIP_IVYBRIDGE_S || \ 329 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2) 330 331 #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ 332 (devid) == PCI_CHIP_VALLEYVIEW_1 || \ 333 (devid) == PCI_CHIP_VALLEYVIEW_2 || \ 334 (devid) == PCI_CHIP_VALLEYVIEW_3) 335 336 #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ 337 (devid) == PCI_CHIP_HASWELL_M_GT1 || \ 338 (devid) == PCI_CHIP_HASWELL_S_GT1 || \ 339 (devid) == PCI_CHIP_HASWELL_B_GT1 || \ 340 (devid) == PCI_CHIP_HASWELL_E_GT1 || \ 341 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ 342 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ 343 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ 344 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ 345 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ 346 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ 347 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ 348 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ 349 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ 350 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ 351 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ 352 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ 353 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ 354 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ 355 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) 356 #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ 357 (devid) == PCI_CHIP_HASWELL_M_GT2 || \ 358 (devid) == PCI_CHIP_HASWELL_S_GT2 || \ 359 (devid) == PCI_CHIP_HASWELL_B_GT2 || \ 360 (devid) == PCI_CHIP_HASWELL_E_GT2 || \ 361 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ 362 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ 363 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ 364 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ 365 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ 366 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ 367 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ 368 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ 369 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ 370 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ 371 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ 372 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ 373 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ 374 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ 375 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) 376 #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ 377 (devid) == PCI_CHIP_HASWELL_M_GT3 || \ 378 (devid) == PCI_CHIP_HASWELL_S_GT3 || \ 379 (devid) == PCI_CHIP_HASWELL_B_GT3 || \ 380 (devid) == PCI_CHIP_HASWELL_E_GT3 || \ 381 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ 382 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ 383 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ 384 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ 385 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ 386 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ 387 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ 388 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ 389 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ 390 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ 391 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ 392 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ 393 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ 394 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ 395 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) 396 397 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ 398 IS_HSW_GT2(devid) || \ 399 IS_HSW_GT3(devid)) 400 401 #define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \ 402 (((devid & 0x00f0) >> 4) > 3) ? 0 : \ 403 ((devid & 0x000f) == BDW_SPARE) ? 1 : \ 404 ((devid & 0x000f) == BDW_ULT) ? 1 : \ 405 ((devid & 0x000f) == BDW_IRIS) ? 1 : \ 406 ((devid & 0x000f) == BDW_SERVER) ? 1 : \ 407 ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \ 408 ((devid & 0x000f) == BDW_ULX) ? 1 : 0) 409 410 #define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \ 411 (devid) == PCI_CHIP_CHERRYVIEW_1 || \ 412 (devid) == PCI_CHIP_CHERRYVIEW_2 || \ 413 (devid) == PCI_CHIP_CHERRYVIEW_3) 414 415 #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ 416 IS_CHERRYVIEW(devid)) 417 418 #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ 419 (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ 420 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \ 421 (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \ 422 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1) 423 424 #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ 425 (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ 426 (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \ 427 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ 428 (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \ 429 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \ 430 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \ 431 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \ 432 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ 433 (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) 434 435 #define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \ 436 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \ 437 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \ 438 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ 439 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) 440 441 #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \ 442 (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ 443 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ 444 (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ 445 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) 446 447 #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \ 448 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \ 449 (devid) == PCI_CHIP_KABYLAKE_ULT_GT1 || \ 450 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \ 451 (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \ 452 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \ 453 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \ 454 (devid) == PCI_CHIP_KABYLAKE_SRV_GT1) 455 456 #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ 457 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ 458 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \ 459 (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ 460 (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ 461 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ 462 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ 463 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) 464 465 #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ 466 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ 467 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2) 468 469 #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4) 470 471 #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \ 472 IS_KBL_GT2(devid) || \ 473 IS_KBL_GT3(devid) || \ 474 IS_KBL_GT4(devid)) 475 476 #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ 477 IS_SKL_GT2(devid) || \ 478 IS_SKL_GT3(devid) || \ 479 IS_SKL_GT4(devid)) 480 481 #define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ 482 (devid) == PCI_CHIP_BROXTON_1 || \ 483 (devid) == PCI_CHIP_BROXTON_2 || \ 484 (devid) == PCI_CHIP_BROXTON_3 || \ 485 (devid) == PCI_CHIP_BROXTON_4) 486 487 #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ 488 (devid) == PCI_CHIP_GLK_2X6) 489 490 #define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ 491 (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ 492 (devid) == PCI_CHIP_COFFEELAKE_S_GT1_3 || \ 493 (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ 494 (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ 495 (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 || \ 496 (devid) == PCI_CHIP_COFFEELAKE_S_GT2_4) 497 498 #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ 499 (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) 500 501 #define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \ 502 (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \ 503 (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ 504 (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \ 505 (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \ 506 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ 507 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ 508 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ 509 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ 510 (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5) 511 512 #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ 513 IS_CFL_H(devid) || \ 514 IS_CFL_U(devid)) 515 516 #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ 517 IS_BROXTON(devid) || \ 518 IS_KABYLAKE(devid) || \ 519 IS_GEMINILAKE(devid) || \ 520 IS_COFFEELAKE(devid)) 521 522 #define IS_CANNONLAKE(devid) ((devid) == PCI_CHIP_CANNONLAKE_0 || \ 523 (devid) == PCI_CHIP_CANNONLAKE_1 || \ 524 (devid) == PCI_CHIP_CANNONLAKE_2 || \ 525 (devid) == PCI_CHIP_CANNONLAKE_3 || \ 526 (devid) == PCI_CHIP_CANNONLAKE_4 || \ 527 (devid) == PCI_CHIP_CANNONLAKE_5 || \ 528 (devid) == PCI_CHIP_CANNONLAKE_6 || \ 529 (devid) == PCI_CHIP_CANNONLAKE_7 || \ 530 (devid) == PCI_CHIP_CANNONLAKE_8 || \ 531 (devid) == PCI_CHIP_CANNONLAKE_9 || \ 532 (devid) == PCI_CHIP_CANNONLAKE_10 || \ 533 (devid) == PCI_CHIP_CANNONLAKE_11 || \ 534 (devid) == PCI_CHIP_CANNONLAKE_12 || \ 535 (devid) == PCI_CHIP_CANNONLAKE_13) 536 537 #define IS_GEN10(devid) (IS_CANNONLAKE(devid)) 538 539 #define IS_9XX(dev) (IS_GEN3(dev) || \ 540 IS_GEN4(dev) || \ 541 IS_GEN5(dev) || \ 542 IS_GEN6(dev) || \ 543 IS_GEN7(dev) || \ 544 IS_GEN8(dev) || \ 545 IS_GEN9(dev) || \ 546 IS_GEN10(dev)) 547 548 #endif /* _INTEL_CHIPSET_H */ 549