Searched refs:ISel (Results 1 – 25 of 89) sorted by relevance
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| /external/llvm/test/CodeGen/X86/ |
| D | insertps-O0-bug.ll | 8 ; scalar load plus scalar_to_vector. This would allow ISel to match the
11 ; However, ISel can only select an INSERTPSrm if folding a load into the operand
23 ; However, ISel would fail to recognize an INSERTPSrm since load folding is
28 ; it assumes ISel to always be able to match an INSERTPSrm. This assumption is
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| D | fast-isel-x86.ll | 101 ; Fast-ISel's arg push is not here:
103 ; SDag-ISel's arg push:
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| D | promote-assert-zext.ll | 7 ; ISel doesn't yet know how to eliminate this extra zero-extend. But until
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| D | isel-optnone.ll | 35 ; Normal ISel will produce 'lea'.
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| D | lea.ll | 15 ; ISel the add of -4 with a neg and use an lea for the rest of the
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | insertps-O0-bug.ll | 8 ; scalar load plus scalar_to_vector. This would allow ISel to match the
11 ; However, ISel can only select an INSERTPSrm if folding a load into the operand
23 ; However, ISel would fail to recognize an INSERTPSrm since load folding is
28 ; it assumes ISel to always be able to match an INSERTPSrm. This assumption is
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| D | O0-pipeline.ll | 16 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
38 ; CHECK-NEXT: Expand ISel Pseudo-instructions
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| D | fast-isel-call-cleanup.ll | 11 ; SDag-ISel's arg mov:
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| D | promote-assert-zext.ll | 7 ; ISel doesn't yet know how to eliminate this extra zero-extend. But until
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| D | lea.ll | 15 ; ISel the add of -4 with a neg and use an lea for the rest of the
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| D | isel-optnone.ll | 35 ; Normal ISel will produce 'lea'.
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| D | addr-mode-matcher.ll | 3 ; This testcase used to hit an assert during ISel. For details, see the big
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | InstructionSelect.cpp | 72 const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector(); in runOnMachineFunction() local
74 assert(ISel && "Cannot work without InstructionSelector"); in runOnMachineFunction()
130 if (!ISel->select(MI, CoverageInfo)) { in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | O0-pipeline.ll | 16 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
42 ; CHECK-NEXT: Expand ISel Pseudo-instructions
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| /external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/ |
| D | delete-node.ll | 4 ; ISel is ignoring dead nodes, though it would be preferable for
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | promote-assert-zext.ll | 7 ; ISel doesn't yet know how to eliminate this extra zero-extend. But until
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| D | lea.ll | 13 ; ISel the add of -4 with a neg and use an lea for the rest of the
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | delete-node.ll | 4 ; ISel is ignoring dead nodes, though it would be preferable for
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | delete-node.ll | 4 ; ISel is ignoring dead nodes, though it would be preferable for
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/pseudo/ |
| D | LDDWRdPtrQ-same-src-dst.mir | 9 # The instruction itself is earlyclobber and so ISel will never produce an
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAGHVX.cpp | 802 HexagonDAGToDAGISel &ISel; member
808 : Lower(getHexagonLowering(G)), ISel(HS), DAG(G), in HvxSelector()
968 ISel.Select(L); in selectVectorConstants()
994 Ops.push_back(ISel.selectUndef(dl, MVT(SVT))); in materialize()
1030 ISel.ReplaceNode(InpN, OutN); in materialize()
1343 Ops.push_back(ISel.selectUndef(dl, ElemTy)); in scalarizeShuffle()
1386 ISel.ReplaceNode(N, LV.getNode()); in scalarizeShuffle()
1411 ISel.Select(S); in scalarizeShuffle()
1970 ISel.ReplaceNode(N, ISel.selectUndef(SDLoc(SN), ResTy).getNode()); in selectShuffle()
2025 ISel.ReplaceNode(N, NewN); in selectRor()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | signbits.ll | 20 ; CHECK: *** MachineFunction at end of ISel ***
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | fast-isel-vaddd.ll | 8 ; Fast-ISel was incorrectly trying to codegen <2 x double> adds and returning only a single vadds
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| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-vaddd.ll | 8 ; Fast-ISel was incorrectly trying to codegen <2 x double> adds and returning only a single vadds
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/X86/ |
| D | dbg-declare-alloca.ll | 5 ; instructions. For SDAG ISel, this test would see an SDNode materializing the
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