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Searched refs:IdxA (Results 1 – 7 of 7) sorted by relevance

/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h563 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, in composeSubRegIndexLaneMask() argument
565 if (!IdxA) in composeSubRegIndexLaneMask()
567 return composeSubRegIndexLaneMaskImpl(IdxA, Mask); in composeSubRegIndexLaneMask()
577 LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, in reverseComposeSubRegIndexLaneMask() argument
579 if (!IdxA) in reverseComposeSubRegIndexLaneMask()
581 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask); in reverseComposeSubRegIndexLaneMask()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h597 LaneBitmask composeSubRegIndexLaneMask(unsigned IdxA, in composeSubRegIndexLaneMask() argument
599 if (!IdxA) in composeSubRegIndexLaneMask()
601 return composeSubRegIndexLaneMaskImpl(IdxA, Mask); in composeSubRegIndexLaneMask()
611 LaneBitmask reverseComposeSubRegIndexLaneMask(unsigned IdxA, in reverseComposeSubRegIndexLaneMask() argument
613 if (!IdxA) in reverseComposeSubRegIndexLaneMask()
615 return reverseComposeSubRegIndexLaneMaskImpl(IdxA, LaneMask); in reverseComposeSubRegIndexLaneMask()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc6054 unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
6063 --IdxA; assert(IdxA < 11);
6065 return Rows[RowMap[IdxA]][IdxB];
6095 LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask…
6096 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
6098 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
6108 LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask …
6109 LaneMask &= getSubRegIndexLaneMask(IdxA);
6110 --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
6112 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc6546 unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
6551 --IdxA; assert(IdxA < 8);
6578 LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)…
6579 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
6581 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
6591 LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask L…
6592 LaneMask &= getSubRegIndexLaneMask(IdxA);
6593 --IdxA; assert(IdxA < 8 && "Subregister index out of bounds");
6595 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc7319 unsigned ARMGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
7334 --IdxA; assert(IdxA < 56);
7336 return Rows[RowMap[IdxA]][IdxB];
7422 LaneBitmask ARMGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)…
7423 --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
7425 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
7435 LaneBitmask ARMGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask L…
7436 LaneMask &= getSubRegIndexLaneMask(IdxA);
7437 --IdxA; assert(IdxA < 56 && "Subregister index out of bounds");
7439 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc8674 unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
8693 --IdxA; assert(IdxA < 99);
8695 return Rows[RowMap[IdxA]][IdxB];
8857 LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneM…
8858 --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
8860 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
8870 LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitma…
8871 LaneMask &= getSubRegIndexLaneMask(IdxA);
8872 --IdxA; assert(IdxA < 99 && "Subregister index out of bounds");
8874 for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) {
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenRegisterInfo.inc4645 unsigned X86GenRegisterInfo::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {
4646 switch (IdxA) {