| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
119 return Imm & 0x7; in getArithShiftValue()
123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { in getExtendType() argument
[all …]
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
119 return Imm & 0x7; in getArithShiftValue()
123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { in getExtendType() argument
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 111 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
112 return ShOp | (Imm << 3); in getSORegOpc()
123 static inline unsigned getSOImmValImm(unsigned Imm) { in getSOImmValImm() argument
124 return Imm & 0xFF; in getSOImmValImm()
128 static inline unsigned getSOImmValRot(unsigned Imm) { in getSOImmValRot() argument
129 return (Imm >> 8) * 2; in getSOImmValRot()
136 static inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
139 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
142 unsigned TZ = CountTrailingZeros_32(Imm); in getSOImmValRotate()
149 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
[all …]
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZTargetTransformInfo.cpp | 34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
46 if (Imm == 0) in getIntImmCost()
49 if (Imm.getBitWidth() <= 64) { in getIntImmCost()
51 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost()
54 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
57 if ((Imm.getZExtValue() & 0xffffffff) == 0) in getIntImmCost()
67 const APInt &Imm, Type *Ty) { in getIntImmCost() argument
90 if (Idx == 0 && Imm.getBitWidth() <= 64) { in getIntImmCost()
95 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
100 if (Idx == 1 && Imm.getBitWidth() <= 64) { in getIntImmCost()
[all …]
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
124 static inline unsigned getSOImmValImm(unsigned Imm) { in getSOImmValImm() argument
125 return Imm & 0xFF; in getSOImmValImm()
129 static inline unsigned getSOImmValRot(unsigned Imm) { in getSOImmValRot() argument
130 return (Imm >> 8) * 2; in getSOImmValRot()
137 static inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
140 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
143 unsigned TZ = countTrailingZeros(Imm); in getSOImmValRotate()
150 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 110 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
111 return ShOp | (Imm << 3); in getSORegOpc()
118 inline unsigned getSOImmValImm(unsigned Imm) { return Imm & 0xFF; } in getSOImmValImm() argument
121 inline unsigned getSOImmValRot(unsigned Imm) { return (Imm >> 8) * 2; } in getSOImmValRot() argument
127 inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
130 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
133 unsigned TZ = countTrailingZeros(Imm); in getSOImmValRotate()
140 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
145 if (Imm & 63U) { in getSOImmValRotate()
146 unsigned TZ2 = countTrailingZeros(Imm & ~63U); in getSOImmValRotate()
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| /external/capstone/arch/ARM/ |
| D | ARMAddressingModes.h | 115 static inline unsigned getSORegOpc(ARM_AM_ShiftOpc ShOp, unsigned Imm) in getSORegOpc() argument
117 return ShOp | (Imm << 3); in getSORegOpc()
132 static inline unsigned getSOImmValImm(unsigned Imm) in getSOImmValImm() argument
134 return Imm & 0xFF; in getSOImmValImm()
139 static inline unsigned getSOImmValRot(unsigned Imm) in getSOImmValRot() argument
141 return (Imm >> 8) * 2; in getSOImmValRot()
148 static inline unsigned getSOImmValRotate(unsigned Imm) in getSOImmValRotate() argument
153 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
156 TZ = CountTrailingZeros_32(Imm); in getSOImmValRotate()
163 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
[all …]
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| /external/llvm/test/MC/Lanai/ |
| D | memory.s | 12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
28 ! CHECK-NEXT: <MCOperand Imm:0>
29 ! CHECK-NEXT: <MCOperand Imm:0>
36 ! CHECK-NEXT: <MCOperand Imm:291>
37 ! CHECK-NEXT: <MCOperand Imm:128>
44 ! CHECK-NEXT: <MCOperand Imm:-4>
45 ! CHECK-NEXT: <MCOperand Imm:128>
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|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Lanai/ |
| D | memory.s | 12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
28 ! CHECK-NEXT: <MCOperand Imm:0>
29 ! CHECK-NEXT: <MCOperand Imm:0>
36 ! CHECK-NEXT: <MCOperand Imm:291>
37 ! CHECK-NEXT: <MCOperand Imm:128>
44 ! CHECK-NEXT: <MCOperand Imm:-4>
45 ! CHECK-NEXT: <MCOperand Imm:128>
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsAnalyzeImmediate.cpp | 29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
43 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL()
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
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|
| D | MipsISelDAGToDAG.h | 88 virtual bool selectVSplat(SDNode *N, APInt &Imm,
91 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
93 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
95 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
97 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
99 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
101 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
103 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
105 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
107 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsAnalyzeImmediate.cpp | 33 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
35 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
36 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
39 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
41 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
42 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
45 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
47 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL()
48 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
52 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
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|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Utils/ |
| D | X86ShuffleDecode.cpp | 23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) { in DecodeINSERTPSMask() argument
31 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
32 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
33 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask()
66 void DecodePSHUFMask(unsigned NElts, unsigned Imm, in DecodePSHUFMask() argument
69 ShuffleMask.push_back(Imm % NElts); in DecodePSHUFMask()
70 Imm /= NElts; in DecodePSHUFMask()
74 void DecodePSHUFHWMask(unsigned Imm, in DecodePSHUFHWMask() argument
81 ShuffleMask.push_back(4+(Imm & 3)); in DecodePSHUFHWMask()
82 Imm >>= 2; in DecodePSHUFHWMask()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 158 ImmOp Imm; member
174 Imm = o.Imm; in RISCVOperand()
187 bool evaluateConstantImm(int64_t &Imm, RISCVMCExpr::VariantKind &VK) const { in evaluateConstantImm()
191 Ret = RE->evaluateAsConstant(Imm); in evaluateConstantImm()
196 Imm = CE->getValue(); in evaluateConstantImm()
204 int64_t Imm; in isBareSimmNLsb0() local
208 bool IsConstantImm = evaluateConstantImm(Imm, VK); in isBareSimmNLsb0()
211 IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm); in isBareSimmNLsb0()
213 IsValid = isShiftedInt<N - 1, 1>(Imm); in isBareSimmNLsb0()
220 int64_t Imm; in isBareSymbol() local
[all …]
|
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 101 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
102 if (Imm != 0) { in printOffset()
307 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) { in printImmediate32() argument
308 int32_t SImm = static_cast<int32_t>(Imm); in printImmediate32()
314 if (Imm == FloatToBits(0.0f)) in printImmediate32()
316 else if (Imm == FloatToBits(1.0f)) in printImmediate32()
318 else if (Imm == FloatToBits(-1.0f)) in printImmediate32()
320 else if (Imm == FloatToBits(0.5f)) in printImmediate32()
322 else if (Imm == FloatToBits(-0.5f)) in printImmediate32()
324 else if (Imm == FloatToBits(2.0f)) in printImmediate32()
[all …]
|
| /external/capstone/arch/AArch64/ |
| D | AArch64AddressingModes.h | 69 static inline AArch64_AM_ShiftExtendType AArch64_AM_getShiftType(unsigned Imm) in AArch64_AM_getShiftType() argument
71 switch ((Imm >> 6) & 0x7) { in AArch64_AM_getShiftType()
82 static inline unsigned AArch64_AM_getShiftValue(unsigned Imm) in AArch64_AM_getShiftValue() argument
84 return Imm & 0x3f; in AArch64_AM_getShiftValue()
92 static inline unsigned AArch64_AM_getArithShiftValue(unsigned Imm) in AArch64_AM_getArithShiftValue() argument
94 return Imm & 0x7; in AArch64_AM_getArithShiftValue()
98 static inline AArch64_AM_ShiftExtendType AArch64_AM_getExtendType(unsigned Imm) in AArch64_AM_getExtendType() argument
101 switch (Imm) { in AArch64_AM_getExtendType()
114 static inline AArch64_AM_ShiftExtendType AArch64_AM_getArithExtendType(unsigned Imm) in AArch64_AM_getArithExtendType() argument
116 return AArch64_AM_getExtendType((Imm >> 3) & 0x7); in AArch64_AM_getArithExtendType()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | macro-aliases.s | 7 # CHECK; Imm:-4
9 # CHECK; Imm:-4
11 # CHECK; Imm:-4
13 # CHECK; Imm:4
15 # CHECK; Imm:4
17 # CHECK; Imm:4
19 # CHECK: Imm:8
22 # CHECK; Imm:-8
24 # CHECK; Imm:-8
26 # CHECK; Imm:-8
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| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 154 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
155 if (!isUInt<N>(Imm)) in decodeUImmOperand()
157 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
162 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
163 if (!isUInt<N>(Imm)) in decodeSImmOperand()
165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
169 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, in decodeAccessRegOperand() argument
172 return decodeUImmOperand<4>(Inst, Imm); in decodeAccessRegOperand()
175 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument
177 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
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| /external/capstone/arch/SystemZ/ |
| D | SystemZDisassembler.c | 96 static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm) in decodeUImmOperand() argument
99 MCOperand_CreateImm0(Inst, Imm); in decodeUImmOperand()
103 static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, unsigned N) in decodeSImmOperand() argument
106 MCOperand_CreateImm0(Inst, SignExtend64(Imm, N)); in decodeSImmOperand()
110 static DecodeStatus decodeAccessRegOperand(MCInst *Inst, uint64_t Imm, in decodeAccessRegOperand() argument
113 return decodeUImmOperand(Inst, Imm); in decodeAccessRegOperand()
116 static DecodeStatus decodeU4ImmOperand(MCInst *Inst, uint64_t Imm, in decodeU4ImmOperand() argument
119 return decodeUImmOperand(Inst, Imm); in decodeU4ImmOperand()
122 static DecodeStatus decodeU6ImmOperand(MCInst *Inst, uint64_t Imm, in decodeU6ImmOperand() argument
125 return decodeUImmOperand(Inst, Imm); in decodeU6ImmOperand()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonInstPrinter.cpp | 130 int64_t Imm; in prints3_6ImmOperand() local
131 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); in prints3_6ImmOperand()
132 Imm = SignExtend64<9>(Imm); in prints3_6ImmOperand()
134 assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO."); in prints3_6ImmOperand()
135 O << formatImm(Imm/64); in prints3_6ImmOperand()
140 int64_t Imm; in prints3_7ImmOperand() local
141 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); in prints3_7ImmOperand()
142 Imm = SignExtend64<10>(Imm); in prints3_7ImmOperand()
144 assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO."); in prints3_7ImmOperand()
145 O << formatImm(Imm/128); in prints3_7ImmOperand()
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|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 53 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand() local
54 if (isInt<16>(Imm) || isUInt<16>(Imm)) in printU16ImmOperand()
55 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
119 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
120 if (Imm != 0) { in printOffset()
129 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffsetS13() local
130 if (Imm != 0) { in printOffsetS13()
398 void AMDGPUInstPrinter::printImmediate16(uint32_t Imm, in printImmediate16() argument
401 int16_t SImm = static_cast<int16_t>(Imm); in printImmediate16()
407 if (Imm == 0x3C00) in printImmediate16()
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 45 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
47 return BaseT::getIntImmCost(Imm, Ty); in getIntImmCost()
55 if (Imm == 0) in getIntImmCost()
58 if (Imm.getBitWidth() <= 64) { in getIntImmCost()
59 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
62 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
64 if ((Imm.getZExtValue() & 0xFFFF) == 0) in getIntImmCost()
74 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, in getIntImmCost() argument
77 return BaseT::getIntImmCost(IID, Idx, Imm, Ty); in getIntImmCost()
92 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) in getIntImmCost()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 172 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
173 if (!isUInt<N>(Imm)) in decodeUImmOperand()
175 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
180 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
181 if (!isUInt<N>(Imm)) in decodeSImmOperand()
183 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
187 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument
189 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
192 static DecodeStatus decodeU2ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU2ImmOperand() argument
194 return decodeUImmOperand<2>(Inst, Imm); in decodeU2ImmOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 63 inline SDValue getI32Imm(unsigned Imm) { in getI32Imm() argument
64 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
69 inline SDValue getI64Imm(uint64_t Imm) { in getI64Imm() argument
70 return CurDAG->getTargetConstant(Imm, MVT::i64); in getI64Imm()
74 inline SDValue getSmallIPtrImm(unsigned Imm) { in getSmallIPtrImm() argument
75 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); in getSmallIPtrImm()
259 static bool isIntS16Immediate(SDNode *N, short &Imm) { in isIntS16Immediate() argument
263 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
265 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
267 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 50 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
52 return BaseT::getIntImmCost(Imm, Ty); in getIntImmCost()
60 if (Imm == 0) in getIntImmCost()
63 if (Imm.getBitWidth() <= 64) { in getIntImmCost()
64 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
67 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
69 if ((Imm.getZExtValue() & 0xFFFF) == 0) in getIntImmCost()
79 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, in getIntImmCost() argument
82 return BaseT::getIntImmCost(IID, Idx, Imm, Ty); in getIntImmCost()
97 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) in getIntImmCost()
[all …]
|