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Searched refs:Imm6 (Results 1 – 5 of 5) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1622 MCOperand &Imm6 = Inst.getOperand(4); in processInstruction() local
1623 Imm6.setExpr(HexagonMCExpr::create( in processInstruction()
1624 MCBinaryExpr::createSub(Imm6.getExpr(), in processInstruction()
1632 TmpInst.addOperand(Imm6); in processInstruction()
1642 MCOperand &Imm6 = Inst.getOperand(4); in processInstruction() local
1643 Imm6.setExpr(HexagonMCExpr::create( in processInstruction()
1644 MCBinaryExpr::createSub(Imm6.getExpr(), in processInstruction()
1652 TmpInst.addOperand(Imm6); in processInstruction()
1662 MCOperand &Imm6 = Inst.getOperand(4); in processInstruction() local
1663 Imm6.setExpr(HexagonMCExpr::create( in processInstruction()
[all …]
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1846 MCOperand &Imm6 = Inst.getOperand(4); in processInstruction() local
1847 Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( in processInstruction()
1848 Imm6.getExpr(), MCConstantExpr::create(1, Context), Context), Context)); in processInstruction()
1854 TmpInst.addOperand(Imm6); in processInstruction()
1865 MCOperand &Imm6 = Inst.getOperand(4); in processInstruction() local
1866 Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( in processInstruction()
1867 Imm6.getExpr(), MCConstantExpr::create(2, Context), Context), Context)); in processInstruction()
1873 TmpInst.addOperand(Imm6); in processInstruction()
1884 MCOperand &Imm6 = Inst.getOperand(4); in processInstruction() local
1885 Imm6.setExpr(HexagonMCExpr::create(MCBinaryExpr::createSub( in processInstruction()
[all …]
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp624 const ConstantInteger32 *Imm6) { in encodeSIMDShiftImm6() argument
625 const IValueT Imm = Imm6->getValue(); in encodeSIMDShiftImm6()
1242 const Operand *OpQm, const IValueT Imm6, in emitSIMDShiftqqc() argument
1250 emitSIMDBase(Opcode | (Imm6 << ElmtShift), mapQRegToDReg(Qd), in emitSIMDShiftqqc()
3372 const IValueT Imm6 = encodeSIMDShiftImm6(ST_Vshr, IceType_i16, 16); in vmulh() local
3375 emitSIMDBase(VshrnOpcode | (Imm6 << ImmShift), Dd, 0, Dd, UseQRegs, in vmulh()
4024 const ConstantInteger32 *Imm6) { in vshlqc() argument
4035 encodeSIMDShiftImm6(ST_Vshl, ElmtTy, Imm6), Vshl); in vshlqc()
4039 const Operand *OpQm, const ConstantInteger32 *Imm6, in vshrqc() argument
4052 encodeSIMDShiftImm6(ST_Vshr, ElmtTy, Imm6), Vshr); in vshrqc()
DIceInstARM32.cpp1042 if (const auto *Imm6 = llvm::dyn_cast<ConstantInteger32>(getSrc(1))) { in emitIAS() local
1043 Asm->vshlqc(ElmtTy, Dest, getSrc(0), Imm6); in emitIAS()
1049 if (const auto *Imm6 = llvm::dyn_cast<ConstantInteger32>(getSrc(1))) { in emitIAS() local
1050 Asm->vshlqc(ElmtTy, Dest, getSrc(0), Imm6); in emitIAS()
1077 const auto *Imm6 = llvm::cast<ConstantInteger32>(getSrc(1)); in emitIAS() local
1081 Asm->vshrqc(ElmtTy, Dest, getSrc(0), Imm6, Sign); in emitIAS()
DIceAssemblerARM32.h864 const Operand *OpQm, const IValueT Imm6,