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Searched refs:InstRef (Results 1 – 23 of 23) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DDispatchStage.h61 bool checkRCU(const InstRef &IR);
62 bool checkPRF(const InstRef &IR);
63 bool checkScheduler(const InstRef &IR);
64 void dispatch(InstRef IR);
67 void notifyInstructionDispatched(const InstRef &IR,
74 bool canDispatch(const InstRef &IR) { in canDispatch()
97 virtual bool execute(InstRef &IR) override final;
98 void notifyDispatchStall(const InstRef &IR, unsigned EventType);
DExecuteStage.cpp39 SmallVector<InstRef, 4> InstructionIDs; in updateSchedulerQueues()
41 for (const InstRef &IR : InstructionIDs) in updateSchedulerQueues()
46 for (const InstRef &IR : InstructionIDs) in updateSchedulerQueues()
52 SmallVector<InstRef, 4> InstructionIDs; in issueReadyInstructions()
53 InstRef IR = HWS.select(); in issueReadyInstructions()
71 for (const InstRef &I : InstructionIDs) in issueReadyInstructions()
99 bool ExecuteStage::execute(InstRef &IR) { in execute()
154 void ExecuteStage::notifyInstructionExecuted(const InstRef &IR) { in notifyInstructionExecuted()
162 void ExecuteStage::notifyInstructionReady(const InstRef &IR) { in notifyInstructionReady()
176 const InstRef &IR, ArrayRef<std::pair<ResourceRef, double>> Used) { in notifyInstructionIssued()
DHWEventListener.h51 HWInstructionEvent(unsigned type, const InstRef &Inst) in HWInstructionEvent()
58 const InstRef &IR;
64 HWInstructionIssuedEvent(const InstRef &IR, in HWInstructionIssuedEvent()
73 HWInstructionDispatchedEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs) in HWInstructionDispatchedEvent()
83 HWInstructionRetiredEvent(const InstRef &IR, llvm::ArrayRef<unsigned> Regs) in HWInstructionRetiredEvent()
108 HWStallEvent(unsigned type, const InstRef &Inst) : Type(type), IR(Inst) {} in HWStallEvent()
114 const InstRef &IR;
DScheduler.h419 InstRef &IR,
435 bool canBeDispatched(const InstRef &IR,
439 bool isReady(const InstRef &IR) const { return LSU->isReady(IR); } in isReady()
444 issueInstruction(InstRef &IR,
452 bool issueImmediately(InstRef &IR);
472 void promoteToReadyQueue(llvm::SmallVectorImpl<InstRef> &Ready);
475 void updatePendingQueue(llvm::SmallVectorImpl<InstRef> &Ready);
478 void updateIssuedQueue(llvm::SmallVectorImpl<InstRef> &Executed);
482 void onInstructionExecuted(const InstRef &IR);
493 bool reserveResources(InstRef &IR);
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DDispatchStage.cpp30 void DispatchStage::notifyInstructionDispatched(const InstRef &IR, in notifyInstructionDispatched()
36 bool DispatchStage::checkPRF(const InstRef &IR) { in checkPRF()
53 bool DispatchStage::checkRCU(const InstRef &IR) { in checkRCU()
62 bool DispatchStage::checkScheduler(const InstRef &IR) { in checkScheduler()
90 void DispatchStage::dispatch(InstRef IR) { in dispatch()
139 bool DispatchStage::execute(InstRef &IR) { in execute()
DLSUnit.h23 class InstRef; variable
132 bool reserve(const InstRef &IR);
141 bool isReady(const InstRef &IR) const;
142 void onInstructionExecuted(const InstRef &IR);
DExecuteStage.h49 virtual bool execute(InstRef &IR) override final;
52 notifyInstructionIssued(const InstRef &IR,
54 void notifyInstructionExecuted(const InstRef &IR);
55 void notifyInstructionReady(const InstRef &IR);
DScheduler.cpp236 bool Scheduler::canBeDispatched(const InstRef &IR, in canBeDispatched()
261 InstRef &IR, in issueInstructionImpl()
280 InstRef &IR, in issueInstruction()
287 void Scheduler::promoteToReadyQueue(SmallVectorImpl<InstRef> &Ready) { in promoteToReadyQueue()
314 InstRef Scheduler::select() { in select()
342 InstRef IR(It->first, It->second); in select()
347 void Scheduler::updatePendingQueue(SmallVectorImpl<InstRef> &Ready) { in updatePendingQueue()
355 void Scheduler::updateIssuedQueue(SmallVectorImpl<InstRef> &Executed) { in updateIssuedQueue()
373 void Scheduler::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
381 bool Scheduler::reserveResources(InstRef &IR) { in reserveResources()
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DLSUnit.cpp54 bool LSUnit::reserve(const InstRef &IR) { in reserve()
76 bool LSUnit::isReady(const InstRef &IR) const { in isReady()
121 void LSUnit::onInstructionExecuted(const InstRef &IR) { in onInstructionExecuted()
DRetireStage.h41 virtual bool execute(InstRef &IR) override final { return true; } in execute()
42 void notifyInstructionRetired(const InstRef &IR);
DRetireControlUnit.h52 InstRef IR;
80 unsigned reserveSlot(const InstRef &IS, unsigned NumMicroOps);
DFetchStage.cpp22 bool FetchStage::execute(InstRef &IR) { in execute()
27 IR = InstRef(SR.first, I.get()); in execute()
DStage.h24 class InstRef; variable
63 virtual bool execute(InstRef &IR) = 0;
DPipeline.cpp43 bool Pipeline::executeStages(InstRef &IR) { in executeStages()
71 InstRef IR; in runCycle()
DInstruction.h377 class InstRef : public std::pair<unsigned, Instruction *> {
379 InstRef() : std::pair<unsigned, Instruction *>(0, nullptr) {} in InstRef() function
380 InstRef(unsigned Index, Instruction *I) in InstRef() function
396 inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const InstRef &IR) {
DInstructionTables.h39 bool execute(InstRef &IR) override final;
DFetchStage.h38 bool execute(InstRef &IR) override final;
DPipeline.h63 bool executeStages(InstRef &IR);
DRetireStage.cpp45 void RetireStage::notifyInstructionRetired(const InstRef &IR) { in notifyInstructionRetired()
DRetireControlUnit.cpp42 unsigned RetireControlUnit::reserveSlot(const InstRef &IR, in reserveSlot()
DInstructionTables.cpp24 bool InstructionTables::execute(InstRef &IR) { in execute()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Vectorize/
DVPlanHCFGBuilder.cpp192 for (Instruction &InstRef : *BB) { in createVPInstructionsForVPBB()
193 Instruction *Inst = &InstRef; in createVPInstructionsForVPBB()
/external/swiftshader/third_party/subzero/src/
DIceCfg.cpp710 for (auto &InstRef : Insts) { in findLoopInvariantInstructions() local
711 auto &Inst = InstRef.get(); in findLoopInvariantInstructions()