| /external/swiftshader/third_party/subzero/pydir/ |
| D | gen_arm32_reg_tables.py | 19 IsStackPtr=0, IsFramePtr=0, IsGPR=0, IsInt=0, IsI64Pair=0, argument
21 assert (not IsInt) or IsGPR
22 assert (not IsI64Pair) or (not IsGPR)
27 assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
28 assert (not IsFramePtr) or IsGPR
29 assert (not IsStackPtr) or IsGPR
82 Reg( 'r0', 0, IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1, Aliases= 'r0, r0r1'),
83 Reg( 'r1', 1, IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1, Aliases= 'r1, r0r1'),
84 Reg( 'r2', 2, IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1, Aliases= 'r2, r2r3'),
85 Reg( 'r3', 3, IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1, Aliases= 'r3, r2r3'),
[all …]
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceRegistersARM32.h | 93 unsigned IsGPR : 1; member
112 return RegTable[RegNum].IsGPR; in isGPRegister()
142 return RegTable[RegNum].IsGPR; in isGPR()
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| D | IceRegistersARM32.def | 7 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsI…
26 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsI…
35 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsI…
70 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsI…
105 //define X(Tag, Encoding, AsmStr, CCArg, IsScratch, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsI…
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| D | IceRegistersMIPS32.h | 75 bool IsGPR = ((int(Reg_GPR_First) <= int(RegNum)) && in isGPRReg() local
79 return IsGPR; in isGPRReg()
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| D | IceAssemblerX86Base.h | 826 static constexpr bool IsGPR = in is8BitRegisterRequiringRex() local
839 return IsGPR && (Reg & 0x04) != 0 && (Reg & 0x08) == 0 && in is8BitRegisterRequiringRex()
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| D | IceTargetLoweringARM32.cpp | 342 if (Entry.IsGPR) { in staticInit()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 879 bool IsGPR; member
909 RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1); in computeCalleeSaveRegisterPairs()
914 if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) || in computeCalleeSaveRegisterPairs()
915 (!RPI.IsGPR && AArch64::FPR64RegClass.contains(NextReg))) in computeCalleeSaveRegisterPairs()
988 if (RPI.IsGPR) in spillCalleeSavedRegisters()
1049 if (RPI.IsGPR) in restoreCalleeSavedRegisters()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1146 bool IsGPR; member
1182 RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1); in computeCalleeSaveRegisterPairs()
1187 if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) || in computeCalleeSaveRegisterPairs()
1188 (!RPI.IsGPR && AArch64::FPR64RegClass.contains(NextReg))) in computeCalleeSaveRegisterPairs()
1286 if (RPI.IsGPR) in spillCalleeSavedRegisters()
1347 if (RPI.IsGPR) in restoreCalleeSavedRegisters()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 232 bool expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, bool Is64FPU,
3282 bool MipsAsmParser::expandLoadImmReal(MCInst &Inst, bool IsSingle, bool IsGPR, in expandLoadImmReal() argument
3313 if (IsGPR) { in expandLoadImmReal()
3360 if (IsGPR) { in expandLoadImmReal()
3585 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) || in expandMemInst() local
3588 if (!IsLoad || !IsGPR || (BaseReg == DstReg)) { in expandMemInst()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2652 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) || in expandLoadInst() local
2657 if (IsGPR && (BaseReg != DstReg)) { in expandLoadInst()
2682 if (IsGPR && (BaseReg != DstReg)) { in expandLoadInst()
|