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Searched refs:IsLP64 (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp46 IsLP64 = STI.isTarget64BitLP64(); in X86FrameLowering()
98 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) { in getSUBriOpcode() argument
99 if (IsLP64) { in getSUBriOpcode()
110 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) { in getADDriOpcode() argument
111 if (IsLP64) { in getADDriOpcode()
130 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) { in getANDriOpcode() argument
131 if (IsLP64) { in getANDriOpcode()
141 static unsigned getLEArOpcode(unsigned IsLP64) { in getLEArOpcode() argument
142 return IsLP64 ? X86::LEA64r : X86::LEA32r; in getLEArOpcode()
2056 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) { in GetScratchRegister() argument
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DX86FrameLowering.h41 bool IsLP64; variable
DX86InstrCompiler.td68 Requires<[IsLP64]>;
72 Requires<[IsLP64]>;
75 (ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
1183 Requires<[IsLP64]>;
1187 Requires<[IsLP64]>;
DX86ISelLowering.cpp23465 const bool IsLP64 = Subtarget.isTarget64BitLP64(); in EmitLoweredSegAlloca() local
23468 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30; in EmitLoweredSegAlloca()
23500 IsLP64 || Subtarget.isTargetNaCl64() ? X86::RSP : X86::ESP; in EmitLoweredSegAlloca()
23515 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) in EmitLoweredSegAlloca()
23517 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr)) in EmitLoweredSegAlloca()
23533 if (IsLP64) { in EmitLoweredSegAlloca()
23564 .addReg(IsLP64 ? X86::RAX : X86::EAX); in EmitLoweredSegAlloca()
DX86InstrInfo.td861 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86FrameLowering.cpp46 IsLP64 = STI.isTarget64BitLP64(); in X86FrameLowering()
96 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) { in getSUBriOpcode() argument
97 if (IsLP64) { in getSUBriOpcode()
108 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) { in getADDriOpcode() argument
109 if (IsLP64) { in getADDriOpcode()
128 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) { in getANDriOpcode() argument
129 if (IsLP64) { in getANDriOpcode()
139 static unsigned getLEArOpcode(unsigned IsLP64) { in getLEArOpcode() argument
140 return IsLP64 ? X86::LEA64r : X86::LEA32r; in getLEArOpcode()
2200 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) { in GetScratchRegister() argument
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DX86FrameLowering.h42 bool IsLP64; variable
DX86InstrCompiler.td71 "#ADJCALLSTACKDOWN", []>, Requires<[IsLP64]>;
75 Requires<[IsLP64]>;
78 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
1168 Requires<[IsLP64]>;
1172 Requires<[IsLP64]>;
DX86ISelLowering.cpp27410 const bool IsLP64 = Subtarget.isTarget64BitLP64(); in EmitLoweredSegAlloca() local
27413 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30; in EmitLoweredSegAlloca()
27445 IsLP64 || Subtarget.isTargetNaCl64() ? X86::RSP : X86::ESP; in EmitLoweredSegAlloca()
27460 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg) in EmitLoweredSegAlloca()
27462 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr)) in EmitLoweredSegAlloca()
27478 if (IsLP64) { in EmitLoweredSegAlloca()
27509 .addReg(IsLP64 ? X86::RAX : X86::EAX); in EmitLoweredSegAlloca()
DX86InstrInfo.td914 def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">;