Searched refs:IsPlainRegister (Results 1 – 10 of 10) sorted by relevance
| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 332 VIXL_CHECK(Operand(x0).IsPlainRegister()); in TEST()
333 VIXL_CHECK(Operand(x1, LSL, 0).IsPlainRegister()); in TEST()
334 VIXL_CHECK(Operand(x2, LSR, 0).IsPlainRegister()); in TEST()
335 VIXL_CHECK(Operand(x3, ASR, 0).IsPlainRegister()); in TEST()
336 VIXL_CHECK(Operand(x4, ROR, 0).IsPlainRegister()); in TEST()
337 VIXL_CHECK(Operand(x5, UXTX).IsPlainRegister()); in TEST()
338 VIXL_CHECK(Operand(x6, SXTX).IsPlainRegister()); in TEST()
339 VIXL_CHECK(Operand(w7).IsPlainRegister()); in TEST()
340 VIXL_CHECK(Operand(w8, LSL, 0).IsPlainRegister()); in TEST()
341 VIXL_CHECK(Operand(w9, LSR, 0).IsPlainRegister()); in TEST()
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| /external/vixl/src/aarch32/ |
| D | operands-aarch32.cc | 533 } else if (operand.IsPlainRegister()) { in operator <<()
553 if (operand.IsPlainRegister()) { in operator <<()
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| D | macro-assembler-aarch32.h | 998 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && in Adc()
1020 rn.Is(rd) && operand.IsPlainRegister() && in Adc()
1075 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && in Add()
1078 (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) && in Add()
1082 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() && in Add()
1105 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && in Add()
1156 if (rd.Is(rn) && operand.IsPlainRegister() && in And()
1172 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && in And()
1193 if (operand.IsPlainRegister() && rd.Is(rn) && in And()
1198 rn.Is(rd) && operand.IsPlainRegister() && in And()
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| D | operands-aarch32.h | 156 bool IsPlainRegister() const { in IsPlainRegister() function
834 bool IsPlainRegister() const { in IsPlainRegister() function
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| D | assembler-aarch32.cc | 1957 if (operand.IsPlainRegister()) { in adc()
2045 if (operand.IsPlainRegister()) { in adcs()
2218 if (operand.IsPlainRegister()) { in add()
2330 if (operand.IsPlainRegister()) { in add()
2412 if (operand.IsPlainRegister()) { in adds()
2729 if (operand.IsPlainRegister()) { in and_()
2817 if (operand.IsPlainRegister()) { in ands()
2909 if (operand.IsPlainRegister()) { in asr()
2978 if (operand.IsPlainRegister()) { in asrs()
3284 if (operand.IsPlainRegister()) { in bic()
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| D | macro-assembler-aarch32.cc | 1793 } else if (operand.IsPlainRegister()) { in Delegate()
2020 if (operand.IsPlainRegister()) { in Delegate()
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| D | disasm-aarch32.h | 479 } else if (operand.IsPlainRegister()) {
503 if (operand.IsPlainRegister()) {
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 1279 if (!left.IsPlainRegister()) { in CselHelper()
1287 if (!right.IsPlainRegister()) { in CselHelper()
1296 VIXL_ASSERT(left.IsPlainRegister() && right.IsPlainRegister()); in CselHelper()
1380 if (left.IsPlainRegister()) { in CselSubHelperRightSmallImmediate()
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| D | operands-aarch64.cc | 329 bool Operand::IsPlainRegister() const { in IsPlainRegister() function in vixl::aarch64::Operand
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| D | operands-aarch64.h | 789 bool IsPlainRegister() const;
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