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Searched refs:IsVec128 (Results 1 – 5 of 5) sorted by relevance

/external/swiftshader/third_party/subzero/pydir/
Dgen_arm32_reg_tables.py20 IsFP32=0, IsFP64=0, IsVec128=0, Aliases=None): argument
25 assert not (IsFP32 and IsVec128)
26 assert not (IsFP64 and IsVec128)
27 assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
180 Reg( 'q0', 0, IsScratch=1, CCArg=1, IsVec128=1, Aliases= 'q0, d0, d1, s0, s1, s2, s3'),
181 Reg( 'q1', 1, IsScratch=1, CCArg=2, IsVec128=1, Aliases= 'q1, d2, d3, s4, s5, s6, s7'),
182 Reg( 'q2', 2, IsScratch=1, CCArg=3, IsVec128=1, Aliases= 'q2, d4, d5, s8, s9, s10, s11'),
183 Reg( 'q3', 3, IsScratch=1, CCArg=4, IsVec128=1, Aliases= 'q3, d6, d7, s12, s13, s14, s15'),
184 Reg( 'q4', 4, IsPreserved=1, IsVec128=1, Aliases= 'q4, d8, d9, s16, s17, s18, s19'),
185 Reg( 'q5', 5, IsPreserved=1, IsVec128=1, Aliases= 'q5, d10, d11, s20, s21, s22, s23'),
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/external/swiftshader/third_party/subzero/src/
DIceRegistersARM32.def7 …h, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
26 …h, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
35 …h, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
70 …h, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
105 …h, IsPreserved, IsStackPtr, IsFramePtr, IsGPR, IsInt, IsI64Pair, IsFP32, IsFP64, IsVec128, Aliases)
DIceRegistersARM32.h98 unsigned IsVec128 : 1; member
202 return RegTable[RegNum].IsVec128; in isEncodedQReg()
DIceTargetLoweringARM32.cpp328 VectorRegisters[i] = Entry.IsVec128; in staticInit()
332 QtoSRegisters[i] = Entry.IsVec128 && Entry.Encoding < EncodedReg_q8; in staticInit()
350 } else if (Entry.IsVec128) { in staticInit()
DIceInstARM32.cpp1570 assert(SrcEntry.IsVec128); in getDRegister()