Searched refs:KS2_DDR3APLLCTL0 (Results 1 – 2 of 2) sorted by relevance
31 [DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},313 reg = KS2_DDR3APLLCTL0; in pll_freq_get()
179 #define KS2_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) macro