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Searched refs:KS2_DDR3A_DDRPHYC (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/board/ti/ks2_evm/
Dddr3_k2g.c172 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1066_2g); in ddr3_init()
175 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g); in ddr3_init()
178 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_512mb); in ddr3_init()
Dddr3_k2hk.c49 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); in ddr3_init()
55 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); in ddr3_init()
Dddr3_k2l.c25 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); in ddr3_init()
Dddr3_k2e.c41 ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); in ddr3_init()
/external/u-boot/arch/arm/mach-keystone/include/mach/
Dhardware.h79 #define KS2_DDR3A_DDRPHYC 0x02329000 macro
/external/u-boot/arch/arm/mach-keystone/
Dddr3.c392 tmp_a = __raw_readl(KS2_DDR3A_DDRPHYC + KS2_DDRPHY_PGSR0_OFFSET); in ddr3_err_reset_workaround()