Searched refs:KS2_DDR3BPLLCTL0 (Results 1 – 2 of 2) sorted by relevance
32 [DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},317 reg = KS2_DDR3BPLLCTL0; in pll_freq_get()
181 #define KS2_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) macro