| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/tools/llvm-exegesis/X86/ |
| D | SnippetGeneratorTest.cpp | 131 TEST_F(LatencySnippetGeneratorTest, LAHF) { in TEST_F() argument
132 const unsigned Opcode = llvm::X86::LAHF; in TEST_F()
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| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| D | isa.hpp | 91 bool LAHF(void) { return CPU_Rep.f_81_ECX_[0]; } in LAHF() function in InstructionSet
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver1.td | 547 //LAHF
548 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
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| D | X86.td | 226 "Support LAHF and SAHF instructions">;
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| D | X86InstrInfo.td | 1745 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags
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| /external/llvm/lib/Target/X86/ |
| D | X86.td | 200 "Support LAHF and SAHF instructions">;
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| D | X86SchedHaswell.td | 502 // LAHF SAHF.
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| D | X86InstrInfo.td | 1588 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
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| D | X86InstrInfo.cpp | 4573 BuildMI(MBB, MI, DL, get(X86::LAHF)); in copyPhysReg()
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 500 #define LAHF CHOICE(lahf, lahf, lahf) macro
1219 #define LAHF lahf macro
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | flags-copy-lowering.mir | 3 # Lower various interesting copy patterns of EFLAGS without using LAHF/SAHF.
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 241 { "sahf", "Support LAHF and SAHF instructions", { X86::FeatureLAHFSAHF }, { } },
5635 {DBGFIELD("LAHF") 1, false, false, 3, 1, 20, 1, 0, 0}, // #923
6851 {DBGFIELD("LAHF") 1, false, false, 93, 4, 1, 1, 0, 0}, // #923
8067 {DBGFIELD("LAHF") 1, false, false, 1, 1, 1, 1, 0, 0}, // #923
9283 {DBGFIELD("LAHF") 1, false, false, 93, 4, 1, 1, 0, 0}, // #923
10499 {DBGFIELD("LAHF") 1, false, false, 382, 3, 1, 1, 0, 0}, // #923
11715 {DBGFIELD("LAHF") 1, false, false, 93, 4, 1, 1, 0, 0}, // #923
12931 {DBGFIELD("LAHF") 1, false, false, 905, 1, 1, 1, 0, 0}, // #923
14147 {DBGFIELD("LAHF") 1, false, false, 93, 4, 1, 1, 0, 0}, // #923
15363 {DBGFIELD("LAHF") 1, false, false, 0, 0, 4, 1, 0, 0}, // #923
|
| D | X86GenAsmWriter.inc | 3088 16944U, // LAHF
18594 0U, // LAHF
34100 0U, // LAHF
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| D | X86GenAsmWriter1.inc | 2768 13734U, // LAHF
18274 0U, // LAHF
|
| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1_reduce.inc | 659 2909U, // LAHF
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| D | X86GenAsmWriter_reduce.inc | 659 4833U, // LAHF
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| D | X86GenAsmWriter.inc | 1195 14409U, // LAHF
7466 0U, // LAHF
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| D | X86GenAsmWriter1.inc | 1195 11535U, // LAHF
7466 0U, // LAHF
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| D | X86GenDisassemblerTables_reduce.inc | 5184 /* LAHF */
26045 0x282, /* LAHF */
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.td | 985 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
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| D | X86GenAsmWriter.inc | 1059 4032U, // LAHF
5931 "_4\000JRCXZ\000JS_1\000JS_4\000LAHF\000LAR16rm\000LAR16rr\000LAR32rm\000"
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| D | X86GenAsmWriter1.inc | 1059 3216U, // LAHF
6674 "_4\000JRCXZ\000JS_1\000JS_4\000LAHF\000LAR16rm\000LAR16rr\000LAR32rm\000"
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| D | X86GenInstrInfo.inc | 1062 LAHF = 1046,
5230 …{ 1046, 0, 0, 0, 0, "LAHF", 0, 0x13e000001ULL, ImplicitList1, ImplicitList27, 0 }, // Inst #1046 …
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| D | X86GenAsmMatcher.inc | 3722 { X86::LAHF, "lahf", Convert, { }, 0},
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| D | X86GenDisassemblerTables.inc | 12571 "LAHF"
47648 0x416 /* LAHF*/
54691 0x416 /* LAHF*/
61832 0x416 /* LAHF*/
68997 0x416 /* LAHF*/
76162 0x416 /* LAHF*/
83210 0x416 /* LAHF*/
90229 0x416 /* LAHF*/
97248 0x416 /* LAHF*/
104267 0x416 /* LAHF*/
[all …]
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