| /external/webp/src/dsp/ |
| D | lossless_neon.c | 266 #define DO_PRED5(LANE) do { \ argument
270 vst1q_lane_u32(&out[i + (LANE)], vreinterpretq_u32_u8(res), (LANE)); \
291 #define DO_PRED67(LANE) do { \ argument
294 vst1q_lane_u32(&out[i + (LANE)], vreinterpretq_u32_u8(res), (LANE)); \
353 #define DO_PRED10(LANE) do { \ argument
357 vst1q_lane_u32(&out[i + (LANE)], vreinterpretq_u32_u8(res), (LANE)); \
381 #define DO_PRED11(LANE) do { \ argument
388 vst1q_lane_u32(&out[i + (LANE)], vreinterpretq_u32_u8(res), (LANE)); \
414 #define DO_PRED12(DIFF, LANE) do { \ argument
418 vadd_u8(pred, (LANE <= 1) ? vget_low_u8(src) : vget_high_u8(src)); \
[all …]
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| D | enc_neon.c | 481 #define LOAD_LANE_16b(VALUE, LANE) do { \ argument
482 (VALUE) = vld1_lane_s16(src, (VALUE), (LANE)); \
655 #define LOAD_LANE_32b(src, VALUE, LANE) \ argument
656 (VALUE) = vld1_lane_u32((const uint32_t*)(src), (VALUE), (LANE))
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| D | lossless_sse2.c | 378 #define DO_PRED12(DIFF, LANE, OUT) do { \ argument
386 #define DO_PRED12_SHIFT(DIFF, LANE) do { \ argument
388 if ((LANE) == 0) (DIFF) = _mm_srli_si128((DIFF), 8); \
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| D | dec_neon.c | 63 #define LOADQ_LANE_32b(VALUE, LANE) do { \ argument
64 (VALUE) = vld1q_lane_u32((const uint32_t*)src, (VALUE), (LANE)); \
311 #define STORE6_LANE(DST, VAL0, VAL1, LANE) do { \ argument
312 vst3_lane_u8((DST) - 3, (VAL0), (LANE)); \
313 vst3_lane_u8((DST) + 0, (VAL1), (LANE)); \
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| /external/libpcap/ |
| D | grammar.h | 135 LANE = 345, enumerator
257 #define LANE 345 macro
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| D | grammar.y | 337 %token LANE LLC METAC BCC SC ILMIC OAMF4EC OAMF4SC
712 atmtype: LANE { $$ = A_LANE; }
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| D | scanner.l | 354 lane return LANE;
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| D | grammar.c | 453 LANE = 345, enumerator
575 #define LANE 345 macro
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| D | scanner.c | 3701 return LANE;
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.readlane.ll | 23 ; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
24 ; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, [[LANE]]
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| D | llvm.amdgcn.writelane.ll | 25 ; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
26 ; CHECK: v_writelane_b32 v{{[0-9]+}}, 12, [[LANE]]
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| /external/v8/src/wasm/ |
| D | wasm-interpreter.cc | 41 #define LANE(i, type) ((sizeof(type.val) / sizeof(type.val[0])) - (i)-1) macro
43 #define LANE(i, type) (i)
1706 Push(WasmValue(ss.val[LANE(imm.lane, ss)])); \ in ExecuteSimdOp()
1722 auto a = s1.val[LANE(i, s1)]; \ in ExecuteSimdOp()
1723 auto b = s2.val[LANE(i, s1)]; \ in ExecuteSimdOp()
1724 res.val[LANE(i, s1)] = expr; \ in ExecuteSimdOp()
1867 s.val[LANE(imm.lane, s)] = new_val.to<ctype>(); \ in ExecuteSimdOp()
1916 ctype a = s.val[LANE(start_index + i, s)]; \ in ExecuteSimdOp()
1917 res.val[LANE(i, res)] = expr; \ in ExecuteSimdOp()
1962 int32_t v = i < count / 2 ? s1.val[LANE(i, s1)] \ in ExecuteSimdOp()
[all …]
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| /external/neon_2_sse/ |
| D | NEON_2_SSE.h | 2308 # define _NEON2SSE_SWITCH16(NAME, a, b, LANE) \ argument
2309 switch(LANE) \
2330 # define _NEON2SSE_SWITCH8(NAME, vec, LANE, p) \ argument
2331 switch(LANE) \
2344 # define _NEON2SSE_SWITCH4(NAME, case0, case1, case2, case3, vec, LANE, p) \ argument
2345 switch(LANE) \
2354 _NEON2SSE_INLINE __m128i _MM_ALIGNR_EPI8(__m128i a, __m128i b, int LANE) in _MM_ALIGNR_EPI8() argument
2356 _NEON2SSE_SWITCH16(_mm_alignr_epi8, a, _NEON2SSE_COMMA b, LANE) in _MM_ALIGNR_EPI8()
2359 _NEON2SSE_INLINE __m128i _MM_INSERT_EPI16(__m128i vec, int p, const int LANE) in _MM_INSERT_EPI16() argument
2361 _NEON2SSE_SWITCH8(_mm_insert_epi16, vec, LANE, _NEON2SSE_COMMA p) in _MM_INSERT_EPI16()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUUsage.rst | 876 registers, or a 64x4 byte single register. In either case use a new LANE op
880 spilling). If choose a wide single register approach then use LANE in
882 the current lane. If the separate register approach then use LANE to select
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| /external/cldr/common/uca/ |
| D | allkeys_DUCET.txt | 3389 26D8 ; [*095D.0020.0002.26D8] # BLACK LEFT LANE MERGE
3390 26D9 ; [*095E.0020.0002.26D9] # WHITE LEFT LANE MERGE
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| D | allkeys_CLDR.txt | 3878 26D8 ; [.0909.0020.0002] # BLACK LEFT LANE MERGE
3879 26D9 ; [.090A.0020.0002] # WHITE LEFT LANE MERGE
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| D | UCA_Rules.txt | 3813 < ⛘ # 5.2 [So] [0909.0020.0002] U+26D8 BLACK LEFT LANE MERGE
3814 < ⛙ # 5.2 [So] [090A.0020.0002] U+26D9 WHITE LEFT LANE MERGE
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| D | FractionalUCA.txt | 6443 26D8; [0C C0 EB, 05, 05] # Zyyy So [0909.0020.0002] * BLACK LEFT LANE MERGE
6445 26D9; [0C C0 F2, 05, 05] # Zyyy So [090A.0020.0002] * WHITE LEFT LANE MERGE
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| /external/cldr/tools/java/org/unicode/cldr/draft/ |
| D | Categories.txt | 8658 26D8 So Symbol Traffic sign BLACK LEFT LANE MERGE
8659 26D9 So Symbol Traffic sign WHITE LEFT LANE MERGE
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| /external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/ |
| D | UnicodeData.txt | 8907 26D8;BLACK LEFT LANE MERGE;So;0;ON;;;;;N;;;;;
8908 26D9;WHITE LEFT LANE MERGE;So;0;ON;;;;;N;;;;;
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| /external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/ |
| D | UnicodeData.txt | 8907 26D8;BLACK LEFT LANE MERGE;So;0;ON;;;;;N;;;;;
8908 26D9;WHITE LEFT LANE MERGE;So;0;ON;;;;;N;;;;;
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| /external/icu/icu4c/source/data/unidata/ |
| D | UnicodeData.txt | 8907 26D8;BLACK LEFT LANE MERGE;So;0;ON;;;;;N;;;;;
8908 26D9;WHITE LEFT LANE MERGE;So;0;ON;;;;;N;;;;;
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| D | ppucd.txt | 11507 cp;26D8;age=5.2;ea=A;lb=ID;na=BLACK LEFT LANE MERGE
11508 cp;26D9;age=5.2;ea=A;lb=ID;na=WHITE LEFT LANE MERGE
|