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Searched refs:LLCR (Results 1 – 16 of 16) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dint-conv-02.ll117 ; Test a case where we spill the source of at least one LLCR. We want
/external/llvm/test/CodeGen/SystemZ/
Dint-conv-02.ll117 ; Test a case where we spill the source of at least one LLCR. We want
/external/v8/src/s390/
Dsimulator-s390.h932 EVALUATE(LLCR);
Dconstants-s390.h1422 V(llcr, LLCR, 0xB994) /* type = RRE LOAD LOGICAL CHARACTER (32<-8) */ \
Dsimulator-s390.cc1220 EvalTable[LLCR] = &Simulator::Evaluate_LLCR; in EvalTableInit()
7221 EVALUATE(LLCR) { in EVALUATE() argument
7222 DCHECK_OPCODE(LLCR); in EVALUATE()
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp972 OpCode = (RISBG.Mask == 0xff ? SystemZ::LLCR : SystemZ::LLHR); in tryRISBGZero()
DSystemZInstrInfo.cpp1061 expandZExtPseudo(MI, SystemZ::LLCR, 8); in expandPostRAPseudo()
DSystemZInstrInfo.td634 // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
637 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp1352 expandZExtPseudo(MI, SystemZ::LLCR, 8); in expandPostRAPseudo()
DSystemZInstrInfo.td620 // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
623 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;
DSystemZScheduleZ196.td223 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;
DSystemZScheduleZEC12.td231 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLCR(Mux)?$")>;
DSystemZScheduleZ13.td250 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
DSystemZScheduleZ14.td251 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLCR(Mux)?$")>;
/external/capstone/arch/SystemZ/
DSystemZGenAsmWriter.inc637 4201737U, // LLCR
DSystemZGenDisassemblerTables.inc665 /* 2529 */ MCD_OPC_Decode, 232, 4, 3, // Opcode: LLCR