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Searched refs:LLHR (Results 1 – 16 of 16) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dint-conv-06.ll117 ; Test a case where we spill the source of at least one LLHR. We want
/external/llvm/test/CodeGen/SystemZ/
Dint-conv-06.ll117 ; Test a case where we spill the source of at least one LLHR. We want
/external/v8/src/s390/
Dsimulator-s390.h933 EVALUATE(LLHR);
Dconstants-s390.h1423 V(llhr, LLHR, 0xB995) /* type = RRE LOAD LOGICAL HALFWORD (32<-16) */ \
Dsimulator-s390.cc1221 EvalTable[LLHR] = &Simulator::Evaluate_LLHR; in EvalTableInit()
7231 EVALUATE(LLHR) { in EVALUATE() argument
7232 DCHECK_OPCODE(LLHR); in EVALUATE()
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp972 OpCode = (RISBG.Mask == 0xff ? SystemZ::LLCR : SystemZ::LLHR); in tryRISBGZero()
DSystemZInstrInfo.cpp1065 expandZExtPseudo(MI, SystemZ::LLHR, 16); in expandPostRAPseudo()
DSystemZInstrInfo.td638 // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
641 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp1356 expandZExtPseudo(MI, SystemZ::LLHR, 16); in expandPostRAPseudo()
DSystemZInstrInfo.td624 // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
627 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
DSystemZScheduleZ196.td224 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;
DSystemZScheduleZEC12.td232 def : InstRW<[WLat1, FXU, NormalGr], (instregex "LLHR(Mux)?$")>;
DSystemZScheduleZ13.td251 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLHR(Mux)?$")>;
DSystemZScheduleZ14.td252 def : InstRW<[WLat1, FXa, NormalGr], (instregex "LLHR(Mux)?$")>;
/external/capstone/arch/SystemZ/
DSystemZGenAsmWriter.inc650 4202021U, // LLHR
DSystemZGenDisassemblerTables.inc668 /* 2544 */ MCD_OPC_Decode, 245, 4, 3, // Opcode: LLHR