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Searched refs:LLHRL (Results 1 – 11 of 11) sorted by relevance

/external/v8/src/s390/
Dsimulator-s390.h653 EVALUATE(LLHRL);
Dconstants-s390.h734 V(llhrl, LLHRL, \
Dsimulator-s390.cc944 EvalTable[LLHRL] = &Simulator::Evaluate_LLHRL; in EvalTableInit()
4927 EVALUATE(LLHRL) { in EVALUATE() argument
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZScheduleZ196.td229 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;
DSystemZScheduleZEC12.td237 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;
DSystemZScheduleZ13.td256 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;
DSystemZScheduleZ14.td257 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LLHRL$")>;
DSystemZInstrInfo.td654 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
/external/capstone/arch/SystemZ/
DSystemZGenAsmWriter.inc651 11541144U, // LLHRL
DSystemZGenDisassemblerTables.inc928 /* 358 */ MCD_OPC_Decode, 246, 4, 105, // Opcode: LLHRL
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.td671 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;