Searched refs:LO32 (Results 1 – 9 of 9) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZOperands.td | 60 def LO32 : SDNodeXForm<imm, [{
157 }], LO32>;
163 }], LO32>;
174 }], LO32>;
197 }], LO32>;
203 }], LO32>;
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| D | SystemZInstrInfo.td | 1111 (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
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| /external/capstone/arch/Mips/ |
| D | MipsGenRegisterInfo.inc | 1256 // LO32 Register Class...
1257 static MCPhysReg LO32[] = {
1261 // LO32 Bit set.
1503 { "LO32", LO32, LO32Bits, 1, sizeof(LO32Bits), Mips_LO32RegClassID, 4, 4, 1, 1 },
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 1751 SDValue LO32; in LowerV2I64Splat() local
1759 LO32 = DAG.getNode(ISD::BITCAST, dl, OpVT, in LowerV2I64Splat()
1775 LO32 = HI32; in LowerV2I64Splat()
1777 HI32 = LO32; in LowerV2I64Splat()
1805 return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32, in LowerV2I64Splat()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 418 def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 433 def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 2212 // LO32 Register Class...
2213 const MCPhysReg LO32[] = {
2217 // LO32 Bit set.
2653 { LO32, LO32Bits, 50, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 4, 1, true },
3918 { 32, 32, 32, VTLists+0 }, // LO32
6631 { // LO32
7125 {1, 1}, // LO32
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| D | MipsGenAsmMatcher.inc | 1920 MCK_LO32, // register class 'LO32'
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 342 def LO32 : SDNodeXForm<imm, [{
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