Searched refs:LPDDR3 (Results 1 – 14 of 14) sorted by relevance
| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk3288.c | 249 case LPDDR3: in pctl_cfg()
318 case LPDDR3: in phy_cfg()
486 if (sdram_params->base.dramtype != LPDDR3) in data_training()
526 if (sdram_params->base.dramtype != LPDDR3) in data_training()
657 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
790 (sdram_params->base.dramtype == LPDDR3 && in sdram_init()
832 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
871 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
892 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
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| D | sdram_rk3399.c | 176 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
311 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
400 else if (sdram_params->base.dramtype == LPDDR3) in phy_io_config()
869 } else if (sdram_params->base.dramtype == LPDDR3) { in data_training()
1047 (dramtype == LPDDR3 && ddr_freq > 933) || in sdram_init()
1068 if (dramtype == LPDDR3) in sdram_init()
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| D | sdram_rk3188.c | 428 if (sdram_params->base.dramtype != LPDDR3) in data_training()
468 if (sdram_params->base.dramtype != LPDDR3) in data_training()
604 if (sdram_params->base.dramtype == LPDDR3) { in sdram_rank_bw_detect()
776 if (sdram_params->base.dramtype == LPDDR3) { in sdram_init()
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| D | sdram_rk322x.c | 222 if (dramtype == LPDDR3) in memory_init()
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| /external/u-boot/doc/device-tree-bindings/ram/ |
| D | st,stm32mp1-ddr.txt | 1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
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| /external/u-boot/drivers/ram/stm32mp1/ |
| D | Kconfig | 10 family: support for LPDDR2, LPDDR3 and DDR3
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | sdram_rk3399.h | 12 LPDDR3 = 0x6, enumerator
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| D | sdram.h | 13 LPDDR3 = 6, enumerator
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| D | sdram_rk322x.h | 13 LPDDR3 = 6, enumerator
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| /external/u-boot/board/google/ |
| D | Kconfig | 48 LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3288-dmc.txt | 108 DRAM type (3=DDR3, 6=LPDDR3)
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| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sun8i_a83t.c | 445 #error Unsupported DRAM type, Please set DRAM type (3:DDR3, 7:LPDDR3) in sunxi_dram_init()
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| D | Kconfig | 347 bool "LPDDR3 with Allwinner stock configuration"
350 This option is the LPDDR3 timing used by the stock boot0 by
369 Set the dram type, 3: DDR3, 7: LPDDR3
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| /external/u-boot/board/hisilicon/hikey/ |
| D | README | 7 * 1GB 800MHz LPDDR3 DRAM
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