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Searched refs:LSU (Results 1 – 25 of 26) sorted by relevance

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/external/mesa3d/src/mesa/sparc/
Dxform.S77 1: ld [%g1 + 0x00], %f0 ! LSU Group
79 ld [%g1 + 0x00], %f8 ! LSU Group
88 st %f1, [%g2 + 0x00] ! LSU
91 st %f2, [%g2 + 0x04] ! LSU
94 st %f3, [%g2 + 0x08] ! LSU
97 st %f4, [%g2 + 0x0c] ! LSU
99 st %f9, [%g2 + 0x10] ! LSU
101 st %f10, [%g2 + 0x14] ! LSU
103 st %f11, [%g2 + 0x18] ! LSU
105 st %f12, [%g2 + 0x1c] ! LSU
[all …]
Dsparc_clip.S106 1: ld [%i0 + 0x0c], %f3 ! LSU Group
107 ld [%i0 + 0x0c], %g5 ! LSU Group
108 ld [%i0 + 0x08], %g4 ! LSU Group
115 ld [%i0 + 0x04], %g4 ! LSU Group
120 ld [%i0 + 0x00], %g4 ! LSU Group
126 ldub [%g1 + %g3], %g3 ! LSU Group
129 stb %g3, [%i2] ! LSU
132 st %g0, [%i5 + 0x00] ! LSU
135 st %g0, [%i5 + 0x04] ! LSU
137 st %g0, [%i5 + 0x08] ! LSU
[all …]
Dnorm.S138 ld [%o3], %f13 ! LSU
247 ld [%o3], %f13 ! LSU
306 st %f3, [%g3 + 0x00] ! LSU
308 st %f5, [%g3 + 0x04] ! LSU
310 st %f7, [%g3 + 0x08] ! LSU
371 st %f3, [%g3 + 0x00] ! LSU
373 st %f5, [%g3 + 0x04] ! LSU
375 st %f7, [%g3 + 0x08] ! LSU
413 st %f3, [%g3 + 0x00] ! LSU
415 st %f5, [%g3 + 0x04] ! LSU
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZScheduleZEC12.td78 def : WriteRes<LSU, [ZEC12_LSUnit]>;
83 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
117 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
118 def : InstRW<[WLat1, LSU, NormalGr], (instregex "(Call)?B(R)?(Asm.*)?$")>;
120 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCTH$")>;
121 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
122 def : InstRW<[WLat1, FXU3, LSU, GroupAlone],
127 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
141 def : InstRW<[WLat1, FXU, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
149 def : InstRW<[WLat1, FXU2, LSU, GroupAlone], (instregex "(Call)?BRASL$")>;
[all …]
DSystemZScheduleZ196.td77 def : WriteRes<LSU, [Z196_LSUnit]>;
82 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
111 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BRC(L)?(Asm.*)?$")>;
112 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?J(G)?(Asm.*)?$")>;
113 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?BC(R)?(Asm.*)?$")>;
114 def : InstRW<[WLat1, LSU, EndGroup], (instregex "(Call)?B(R)?(Asm.*)?$")>;
115 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BRCT(G|H)?$")>;
116 def : InstRW<[WLat1, FXU, LSU, GroupAlone], (instregex "BCT(G)?(R)?$")>;
117 def : InstRW<[WLat1, FXU3, LSU, GroupAlone],
121 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
[all …]
DSystemZScheduleZ13.td79 def : WriteRes<LSU, [Z13_LSUnit]>;
89 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
153 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
174 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
175 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
188 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
189 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
190 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
191 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
201 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LZR(F|G)$")>;
[all …]
DSystemZScheduleZ14.td79 def : WriteRes<LSU, [Z14_LSUnit]>;
89 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
131 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "BI(C)?(Asm.*)?$")>;
154 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "CL(G)?T(Asm.*)?$")>;
175 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MV(G|H)?HI$")>;
176 def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "MVI(Y)?$")>;
189 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L(Y|FH|RL|Mux)?$")>;
190 def : InstRW<[LSULatency, LSULatency, LSU, NormalGr], (instregex "LCBB$")>;
191 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "LG(RL)?$")>;
192 def : InstRW<[LSULatency, LSU, NormalGr], (instregex "L128$")>;
[all …]
DSystemZSchedule.td21 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
28 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
42 def "LSU"#Num : SchedWrite;
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DScheduler.cpp241 if (Desc.MayLoad && LSU->isLQFull()) in canBeDispatched()
243 else if (Desc.MayStore && LSU->isSQFull()) in canBeDispatched()
301 if (!IS->isReady() || (IsMemOp && !LSU->isReady({IID, IS}))) { in promoteToReadyQueue()
374 LSU->onInstructionExecuted(IR); in onInstructionExecuted()
383 const bool Reserved = LSU->reserve(IR); in reserveResources()
384 if (!IR.getInstruction()->isReady() || (Reserved && !LSU->isReady(IR))) { in reserveResources()
DScheduler.h410 std::unique_ptr<LSUnit> LSU; variable
426 LSU(llvm::make_unique<LSUnit>(LoadQueueSize, StoreQueueSize, in Scheduler()
439 bool isReady(const InstRef &IR) const { return LSU->isReady(IR); } in isReady()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td46 // Each LSU pipeline can also execute FX add and logical instructions.
47 // Each LSU pipeline can complete a load or store in one cycle.
49 // Each store is broken into two parts, AGEN goes to the LSU while a
DPPCScheduleE500.td26 // 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
32 def E500_LSU_0 : FuncUnit; // LSU pipeline
DPPCScheduleP8.td28 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
250 // op is issued to the LSU, and the data op (register fetch) is issued
387 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
DPPCScheduleE500mc.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
36 def E500mc_LSU_0 : FuncUnit; // LSU pipeline
DPPCScheduleE5500.td27 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
39 def E5500_LSU_0 : FuncUnit; // LSU pipeline
DPPCInstrInfo.td2393 /// that they will fill slots (which could cause the load of a LSU reject to
/external/llvm/lib/Target/PowerPC/
DPPCScheduleP7.td46 // Each LSU pipeline can also execute FX add and logical instructions.
47 // Each LSU pipeline can complete a load or store in one cycle.
49 // Each store is broken into two parts, AGEN goes to the LSU while a
DPPCScheduleP8.td28 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
250 // op is issued to the LSU, and the data op (register fetch) is issued
387 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
DPPCScheduleE500mc.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
36 def E500_LSU_0 : FuncUnit; // LSU pipeline
DPPCScheduleE5500.td27 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
39 def E5500_LSU_0 : FuncUnit; // LSU pipeline
DPPCInstrInfo.td2159 /// that they will fill slots (which could cause the load of a LSU reject to
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.td1006 /// that they will fill slots (which could cause the load of a LSU reject to
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
DsubdivisionData.txt128 AO-LSU Lunda Sul
D2013-1_UNLOCODE_CodeListPart2.csv11651 ,"IT","LSU","Castelletto Stura","Castelletto Stura","CN","--3-----","RQ","1001",,"4426N 00738E",
20080 ,"MY","LSU","Long Sukang","Long Sukang",,"---4----","AI","9601",,,
22669 ,"NO","LSU","Lys�ysund","Lysoysund","16","1-------","RQ","0901",,"6353N 00952E",
D2013-1_UNLOCODE_CodeListPart1.csv7124 ,"BR","LSU","Laranjeiras do Sul","Laranjeiras do Sul","PR","--3-----","RQ","0607",,,
21769 ,"DE","LSU","Ludwigsau","Ludwigsau","HE","123-----","RL","0601",,"5053N 00944E",
26815 "X","EE","LSU","Lohusuu","Lohusuu","44","1-------","XX","1301",,"5857N 02703E","Use EE LHU"
29304 "+","ES","LSU","La Ca�ada de San Urbano","La Canada de San Urbano","AL","--3-----","RL","1301",,"36…
36977 ,"FR","LSU","La Selle-en-Luitr�","La Selle-en-Luitre","35","--3-----","RL","0407",,"4818N 00108W",

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