• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __ASM_PPC_FSL_LBC_H
7 #define __ASM_PPC_FSL_LBC_H
8 
9 #include <config.h>
10 #include <common.h>
11 
12 #ifdef CONFIG_MPC85xx
13 void lbc_sdram_init(void);
14 #endif
15 
16 /* BR - Base Registers
17  */
18 #define BR0				0x5000		/* Register offset to immr */
19 #define BR1				0x5008
20 #define BR2				0x5010
21 #define BR3				0x5018
22 #define BR4				0x5020
23 #define BR5				0x5028
24 #define BR6				0x5030
25 #define BR7				0x5038
26 
27 #define BR_BA				0xFFFF8000
28 #define BR_BA_SHIFT			15
29 #define BR_XBA				0x00006000
30 #define BR_XBA_SHIFT			13
31 #define BR_PS				0x00001800
32 #define BR_PS_SHIFT			11
33 #define BR_PS_8				0x00000800	/* Port Size 8 bit */
34 #define BR_PS_16			0x00001000	/* Port Size 16 bit */
35 #define BR_PS_32			0x00001800	/* Port Size 32 bit */
36 #define BR_DECC				0x00000600
37 #define BR_DECC_SHIFT			9
38 #define BR_DECC_OFF			0x00000000
39 #define BR_DECC_CHK			0x00000200
40 #define BR_DECC_CHK_GEN			0x00000400
41 #define BR_WP				0x00000100
42 #define BR_WP_SHIFT			8
43 #define BR_MSEL				0x000000E0
44 #define BR_MSEL_SHIFT			5
45 #define BR_MS_GPCM			0x00000000	/* GPCM */
46 #if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360)
47 #define BR_MS_FCM			0x00000020	/* FCM */
48 #endif
49 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360)
50 #define BR_MS_SDRAM			0x00000060	/* SDRAM */
51 #elif defined(CONFIG_MPC85xx)
52 #define BR_MS_SDRAM			0x00000000	/* SDRAM */
53 #endif
54 #define BR_MS_UPMA			0x00000080	/* UPMA */
55 #define BR_MS_UPMB			0x000000A0	/* UPMB */
56 #define BR_MS_UPMC			0x000000C0	/* UPMC */
57 #if !defined(CONFIG_MPC834x)
58 #define BR_ATOM				0x0000000C
59 #define BR_ATOM_SHIFT			2
60 #endif
61 #define BR_V				0x00000001
62 #define BR_V_SHIFT			0
63 
64 #define BR_UPMx_TO_MSEL(x)		((x + 4) << BR_MSEL_SHIFT)
65 
66 #define UPMA			0
67 #define UPMB			1
68 #define UPMC			2
69 
70 #if defined(CONFIG_MPC834x)
71 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
72 #else
73 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
74 #endif
75 
76 /* Convert an address into the right format for the BR registers */
77 #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
78 #define BR_PHYS_ADDR(x)	\
79 	((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
80 #else
81 #define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
82 #endif
83 
84 /* OR - Option Registers
85  */
86 #define OR0				0x5004		/* Register offset to immr */
87 #define OR1				0x500C
88 #define OR2				0x5014
89 #define OR3				0x501C
90 #define OR4				0x5024
91 #define OR5				0x502C
92 #define OR6				0x5034
93 #define OR7				0x503C
94 
95 #define OR_GPCM_AM			0xFFFF8000
96 #define OR_GPCM_AM_SHIFT		15
97 #define OR_GPCM_XAM			0x00006000
98 #define OR_GPCM_XAM_SHIFT		13
99 #define OR_GPCM_BCTLD			0x00001000
100 #define OR_GPCM_BCTLD_SHIFT		12
101 #define OR_GPCM_CSNT			0x00000800
102 #define OR_GPCM_CSNT_SHIFT		11
103 #define OR_GPCM_ACS			0x00000600
104 #define OR_GPCM_ACS_SHIFT		9
105 #define OR_GPCM_ACS_DIV2		0x00000600
106 #define OR_GPCM_ACS_DIV4		0x00000400
107 #define OR_GPCM_XACS			0x00000100
108 #define OR_GPCM_XACS_SHIFT		8
109 #define OR_GPCM_SCY			0x000000F0
110 #define OR_GPCM_SCY_SHIFT		4
111 #define OR_GPCM_SCY_1			0x00000010
112 #define OR_GPCM_SCY_2			0x00000020
113 #define OR_GPCM_SCY_3			0x00000030
114 #define OR_GPCM_SCY_4			0x00000040
115 #define OR_GPCM_SCY_5			0x00000050
116 #define OR_GPCM_SCY_6			0x00000060
117 #define OR_GPCM_SCY_7			0x00000070
118 #define OR_GPCM_SCY_8			0x00000080
119 #define OR_GPCM_SCY_9			0x00000090
120 #define OR_GPCM_SCY_10			0x000000a0
121 #define OR_GPCM_SCY_11			0x000000b0
122 #define OR_GPCM_SCY_12			0x000000c0
123 #define OR_GPCM_SCY_13			0x000000d0
124 #define OR_GPCM_SCY_14			0x000000e0
125 #define OR_GPCM_SCY_15			0x000000f0
126 #define OR_GPCM_SETA			0x00000008
127 #define OR_GPCM_SETA_SHIFT		3
128 #define OR_GPCM_TRLX			0x00000004
129 #define OR_GPCM_TRLX_SHIFT		2
130 #define OR_GPCM_TRLX_CLEAR		0x00000000
131 #define OR_GPCM_TRLX_SET		0x00000004
132 #define OR_GPCM_EHTR			0x00000002
133 #define OR_GPCM_EHTR_SHIFT		1
134 #define OR_GPCM_EHTR_CLEAR		0x00000000
135 #define OR_GPCM_EHTR_SET		0x00000002
136 #if !defined(CONFIG_MPC8308)
137 #define OR_GPCM_EAD			0x00000001
138 #define OR_GPCM_EAD_SHIFT		0
139 #endif
140 
141 /* helpers to convert values into an OR address mask (GPCM mode) */
142 #define P2SZ_TO_AM(s)	((~((s) - 1)) & 0xffff8000)	/* must be pow of 2 */
143 #define MEG_TO_AM(m)	P2SZ_TO_AM((m) << 20)
144 
145 #define OR_FCM_AM			0xFFFF8000
146 #define OR_FCM_AM_SHIFT				15
147 #define OR_FCM_XAM			0x00006000
148 #define OR_FCM_XAM_SHIFT		13
149 #define OR_FCM_BCTLD			0x00001000
150 #define OR_FCM_BCTLD_SHIFT			12
151 #define OR_FCM_PGS			0x00000400
152 #define OR_FCM_PGS_SHIFT			10
153 #define OR_FCM_CSCT			0x00000200
154 #define OR_FCM_CSCT_SHIFT			 9
155 #define OR_FCM_CST			0x00000100
156 #define OR_FCM_CST_SHIFT			 8
157 #define OR_FCM_CHT			0x00000080
158 #define OR_FCM_CHT_SHIFT			 7
159 #define OR_FCM_SCY			0x00000070
160 #define OR_FCM_SCY_SHIFT			 4
161 #define OR_FCM_SCY_1			0x00000010
162 #define OR_FCM_SCY_2			0x00000020
163 #define OR_FCM_SCY_3			0x00000030
164 #define OR_FCM_SCY_4			0x00000040
165 #define OR_FCM_SCY_5			0x00000050
166 #define OR_FCM_SCY_6			0x00000060
167 #define OR_FCM_SCY_7			0x00000070
168 #define OR_FCM_RST			0x00000008
169 #define OR_FCM_RST_SHIFT			 3
170 #define OR_FCM_TRLX			0x00000004
171 #define OR_FCM_TRLX_SHIFT			 2
172 #define OR_FCM_EHTR			0x00000002
173 #define OR_FCM_EHTR_SHIFT			 1
174 
175 #define OR_UPM_AM			0xFFFF8000
176 #define OR_UPM_AM_SHIFT			15
177 #define OR_UPM_XAM			0x00006000
178 #define OR_UPM_XAM_SHIFT		13
179 #define OR_UPM_BCTLD			0x00001000
180 #define OR_UPM_BCTLD_SHIFT		12
181 #define OR_UPM_BI			0x00000100
182 #define OR_UPM_BI_SHIFT			8
183 #define OR_UPM_TRLX			0x00000004
184 #define OR_UPM_TRLX_SHIFT		2
185 #define OR_UPM_EHTR			0x00000002
186 #define OR_UPM_EHTR_SHIFT		1
187 #define OR_UPM_EAD			0x00000001
188 #define OR_UPM_EAD_SHIFT		0
189 
190 #define OR_SDRAM_AM			0xFFFF8000
191 #define OR_SDRAM_AM_SHIFT		15
192 #define OR_SDRAM_XAM			0x00006000
193 #define OR_SDRAM_XAM_SHIFT		13
194 #define OR_SDRAM_COLS			0x00001C00
195 #define OR_SDRAM_COLS_SHIFT		10
196 #define OR_SDRAM_MIN_COLS		7
197 #define OR_SDRAM_ROWS			0x000001C0
198 #define OR_SDRAM_ROWS_SHIFT		6
199 #define OR_SDRAM_MIN_ROWS		9
200 #define OR_SDRAM_PMSEL			0x00000020
201 #define OR_SDRAM_PMSEL_SHIFT		5
202 #define OR_SDRAM_EAD			0x00000001
203 #define OR_SDRAM_EAD_SHIFT		0
204 
205 #define OR_AM_32KB			0xFFFF8000
206 #define OR_AM_64KB			0xFFFF0000
207 #define OR_AM_128KB			0xFFFE0000
208 #define OR_AM_256KB			0xFFFC0000
209 #define OR_AM_512KB			0xFFF80000
210 #define OR_AM_1MB			0xFFF00000
211 #define OR_AM_2MB			0xFFE00000
212 #define OR_AM_4MB			0xFFC00000
213 #define OR_AM_8MB			0xFF800000
214 #define OR_AM_16MB			0xFF000000
215 #define OR_AM_32MB			0xFE000000
216 #define OR_AM_64MB			0xFC000000
217 #define OR_AM_128MB			0xF8000000
218 #define OR_AM_256MB			0xF0000000
219 #define OR_AM_512MB			0xE0000000
220 #define OR_AM_1GB			0xC0000000
221 #define OR_AM_2GB			0x80000000
222 #define OR_AM_4GB			0x00000000
223 
224 /* MxMR - UPM Machine A/B/C Mode Registers
225  */
226 #define MxMR_MAD_MSK		0x0000003f /* Machine Address Mask	   */
227 #define MxMR_TLFx_MSK		0x000003c0 /* Refresh Loop Field Mask	   */
228 #define MxMR_WLFx_MSK		0x00003c00 /* Write Loop Field Mask	   */
229 #define MxMR_WLFx_1X		0x00000400 /*	executed 1 time		   */
230 #define MxMR_WLFx_2X		0x00000800 /*	executed 2 times	   */
231 #define MxMR_WLFx_3X		0x00000c00 /*	executed 3 times	   */
232 #define MxMR_WLFx_4X		0x00001000 /*	executed 4 times	   */
233 #define MxMR_WLFx_5X		0x00001400 /*	executed 5 times	   */
234 #define MxMR_WLFx_6X		0x00001800 /*	executed 6 times	   */
235 #define MxMR_WLFx_7X		0x00001c00 /*	executed 7 times	   */
236 #define MxMR_WLFx_8X		0x00002000 /*	executed 8 times	   */
237 #define MxMR_WLFx_9X		0x00002400 /*	executed 9 times	   */
238 #define MxMR_WLFx_10X		0x00002800 /*	executed 10 times	   */
239 #define MxMR_WLFx_11X		0x00002c00 /*	executed 11 times	   */
240 #define MxMR_WLFx_12X		0x00003000 /*	executed 12 times	   */
241 #define MxMR_WLFx_13X		0x00003400 /*	executed 13 times	   */
242 #define MxMR_WLFx_14X		0x00003800 /*	executed 14 times	   */
243 #define MxMR_WLFx_15X		0x00003c00 /*	executed 15 times	   */
244 #define MxMR_WLFx_16X		0x00000000 /*	executed 16 times	   */
245 #define MxMR_RLFx_MSK		0x0003c000 /* Read Loop Field Mask	   */
246 #define MxMR_GPL_x4DIS		0x00040000 /* GPL_A4 Ouput Line Disable	   */
247 #define MxMR_G0CLx_MSK		0x00380000 /* General Line 0 Control Mask  */
248 #define MxMR_DSx_1_CYCL		0x00000000 /* 1 cycle Disable Period	   */
249 #define MxMR_DSx_2_CYCL		0x00400000 /* 2 cycle Disable Period	   */
250 #define MxMR_DSx_3_CYCL		0x00800000 /* 3 cycle Disable Period	   */
251 #define MxMR_DSx_4_CYCL		0x00c00000 /* 4 cycle Disable Period	   */
252 #define MxMR_DSx_MSK		0x00c00000 /* Disable Timer Period Mask	   */
253 #define MxMR_AMx_MSK		0x07000000 /* Addess Multiplex Size Mask   */
254 #define MxMR_UWPL		0x08000000 /* LUPWAIT Polarity Mask	   */
255 #define MxMR_OP_NORM		0x00000000 /* Normal Operation		   */
256 #define MxMR_OP_WARR		0x10000000 /* Write to Array		   */
257 #define MxMR_OP_RARR		0x20000000 /* Read from Array		   */
258 #define MxMR_OP_RUNP		0x30000000 /* Run Pattern		   */
259 #define MxMR_OP_MSK		0x30000000 /* Command Opcode Mask	   */
260 #define MxMR_RFEN		0x40000000 /* Refresh Enable		   */
261 #define MxMR_BSEL		0x80000000 /* Bus Select		   */
262 
263 #define LBLAWAR_EN			0x80000000
264 #define LBLAWAR_4KB			0x0000000B
265 #define LBLAWAR_8KB			0x0000000C
266 #define LBLAWAR_16KB			0x0000000D
267 #define LBLAWAR_32KB			0x0000000E
268 #define LBLAWAR_64KB			0x0000000F
269 #define LBLAWAR_128KB			0x00000010
270 #define LBLAWAR_256KB			0x00000011
271 #define LBLAWAR_512KB			0x00000012
272 #define LBLAWAR_1MB			0x00000013
273 #define LBLAWAR_2MB			0x00000014
274 #define LBLAWAR_4MB			0x00000015
275 #define LBLAWAR_8MB			0x00000016
276 #define LBLAWAR_16MB			0x00000017
277 #define LBLAWAR_32MB			0x00000018
278 #define LBLAWAR_64MB			0x00000019
279 #define LBLAWAR_128MB			0x0000001A
280 #define LBLAWAR_256MB			0x0000001B
281 #define LBLAWAR_512MB			0x0000001C
282 #define LBLAWAR_1GB			0x0000001D
283 #define LBLAWAR_2GB			0x0000001E
284 
285 /* LBCR - Local Bus Configuration Register
286  */
287 #define LBCR_LDIS			0x80000000
288 #define LBCR_LDIS_SHIFT			31
289 #define LBCR_BCTLC			0x00C00000
290 #define LBCR_BCTLC_SHIFT		22
291 #define LBCR_LPBSE			0x00020000
292 #define LBCR_LPBSE_SHIFT		17
293 #define LBCR_EPAR			0x00010000
294 #define LBCR_EPAR_SHIFT			16
295 #define LBCR_BMT			0x0000FF00
296 #define LBCR_BMT_SHIFT			8
297 #define LBCR_BMTPS	 		0x0000000F
298 #define LBCR_BMTPS_SHIFT 		0
299 
300 /* LCRR - Clock Ratio Register
301  */
302 #define LCRR_DBYP			0x80000000
303 #define LCRR_DBYP_SHIFT			31
304 #define LCRR_BUFCMDC			0x30000000
305 #define LCRR_BUFCMDC_SHIFT		28
306 #define LCRR_BUFCMDC_1			0x10000000
307 #define LCRR_BUFCMDC_2			0x20000000
308 #define LCRR_BUFCMDC_3			0x30000000
309 #define LCRR_BUFCMDC_4			0x00000000
310 #define LCRR_ECL			0x03000000
311 #define LCRR_ECL_SHIFT			24
312 #define LCRR_ECL_4			0x00000000
313 #define LCRR_ECL_5			0x01000000
314 #define LCRR_ECL_6			0x02000000
315 #define LCRR_ECL_7			0x03000000
316 #define LCRR_EADC			0x00030000
317 #define LCRR_EADC_SHIFT			16
318 #define LCRR_EADC_1			0x00010000
319 #define LCRR_EADC_2			0x00020000
320 #define LCRR_EADC_3			0x00030000
321 #define LCRR_EADC_4			0x00000000
322 /* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
323  * should always be zero on older parts that have a four bit CLKDIV.
324  */
325 #define LCRR_CLKDIV			0x0000001F
326 #define LCRR_CLKDIV_SHIFT		0
327 #if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
328 	defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) || \
329 	defined(CONFIG_ARCH_MPC8560)
330 #define LCRR_CLKDIV_2			0x00000002
331 #define LCRR_CLKDIV_4			0x00000004
332 #define LCRR_CLKDIV_8			0x00000008
333 #elif defined(CONFIG_FSL_CORENET)
334 #define LCRR_CLKDIV_8			0x00000002
335 #define LCRR_CLKDIV_16			0x00000004
336 #define LCRR_CLKDIV_32			0x00000008
337 #else
338 #define LCRR_CLKDIV_4			0x00000002
339 #define LCRR_CLKDIV_8			0x00000004
340 #define LCRR_CLKDIV_16			0x00000008
341 #endif
342 
343 /* LTEDR - Transfer Error Check Disable Register
344  */
345 #define LTEDR_BMD	0x80000000 /* Bus monitor disable				*/
346 #define LTEDR_PARD	0x20000000 /* Parity error checking disabled			*/
347 #define LTEDR_WPD	0x04000000 /* Write protect error checking diable		*/
348 #define LTEDR_WARA	0x00800000 /* Write-after-read-atomic error checking diable	*/
349 #define LTEDR_RAWA	0x00400000 /* Read-after-write-atomic error checking disable	*/
350 #define LTEDR_CSD	0x00080000 /* Chip select error checking disable		*/
351 
352 /* FMR - Flash Mode Register
353  */
354 #define FMR_CWTO               0x0000F000
355 #define FMR_CWTO_SHIFT         12
356 #define FMR_BOOT               0x00000800
357 #define FMR_ECCM               0x00000100
358 #define FMR_AL                 0x00000030
359 #define FMR_AL_SHIFT           4
360 #define FMR_OP                 0x00000003
361 #define FMR_OP_SHIFT           0
362 
363 /* FIR - Flash Instruction Register
364  */
365 #define FIR_OP0                        0xF0000000
366 #define FIR_OP0_SHIFT          28
367 #define FIR_OP1                        0x0F000000
368 #define FIR_OP1_SHIFT          24
369 #define FIR_OP2                        0x00F00000
370 #define FIR_OP2_SHIFT          20
371 #define FIR_OP3                        0x000F0000
372 #define FIR_OP3_SHIFT          16
373 #define FIR_OP4                        0x0000F000
374 #define FIR_OP4_SHIFT          12
375 #define FIR_OP5                        0x00000F00
376 #define FIR_OP5_SHIFT          8
377 #define FIR_OP6                        0x000000F0
378 #define FIR_OP6_SHIFT          4
379 #define FIR_OP7                        0x0000000F
380 #define FIR_OP7_SHIFT          0
381 #define FIR_OP_NOP             0x0 /* No operation and end of sequence */
382 #define FIR_OP_CA              0x1 /* Issue current column address */
383 #define FIR_OP_PA              0x2 /* Issue current block+page address */
384 #define FIR_OP_UA              0x3 /* Issue user defined address */
385 #define FIR_OP_CM0             0x4 /* Issue command from FCR[CMD0] */
386 #define FIR_OP_CM1             0x5 /* Issue command from FCR[CMD1] */
387 #define FIR_OP_CM2             0x6 /* Issue command from FCR[CMD2] */
388 #define FIR_OP_CM3             0x7 /* Issue command from FCR[CMD3] */
389 #define FIR_OP_WB              0x8 /* Write FBCR bytes from FCM buffer */
390 #define FIR_OP_WS              0x9 /* Write 1 or 2 bytes from MDR[AS] */
391 #define FIR_OP_RB              0xA /* Read FBCR bytes to FCM buffer */
392 #define FIR_OP_RS              0xB /* Read 1 or 2 bytes to MDR[AS] */
393 #define FIR_OP_CW0             0xC /* Wait then issue FCR[CMD0] */
394 #define FIR_OP_CW1             0xD /* Wait then issue FCR[CMD1] */
395 #define FIR_OP_RBW             0xE /* Wait then read FBCR bytes */
396 #define FIR_OP_RSW             0xF /* Wait then read 1 or 2 bytes */
397 
398 /* FCR - Flash Command Register
399  */
400 #define FCR_CMD0               0xFF000000
401 #define FCR_CMD0_SHIFT         24
402 #define FCR_CMD1               0x00FF0000
403 #define FCR_CMD1_SHIFT         16
404 #define FCR_CMD2               0x0000FF00
405 #define FCR_CMD2_SHIFT         8
406 #define FCR_CMD3               0x000000FF
407 #define FCR_CMD3_SHIFT         0
408 /* FBAR - Flash Block Address Register
409  */
410 #define FBAR_BLK               0x00FFFFFF
411 
412 /* FPAR - Flash Page Address Register
413  */
414 #define FPAR_SP_PI             0x00007C00
415 #define FPAR_SP_PI_SHIFT       10
416 #define FPAR_SP_MS             0x00000200
417 #define FPAR_SP_CI             0x000001FF
418 #define FPAR_SP_CI_SHIFT       0
419 #define FPAR_LP_PI             0x0003F000
420 #define FPAR_LP_PI_SHIFT       12
421 #define FPAR_LP_MS             0x00000800
422 #define FPAR_LP_CI             0x000007FF
423 #define FPAR_LP_CI_SHIFT       0
424 
425 /* LSDMR - SDRAM Machine Mode Register
426  */
427 #define LSDMR_RFEN	(1 << (31 -  1))
428 #define LSDMR_BSMA1516	(3 << (31 - 10))
429 #define LSDMR_BSMA1617	(4 << (31 - 10))
430 #define LSDMR_RFCR5	(3 << (31 - 16))
431 #define LSDMR_RFCR16	(7 << (31 - 16))
432 #define LSDMR_PRETOACT3 (3 << (31 - 19))
433 #define LSDMR_PRETOACT7	(7 << (31 - 19))
434 #define LSDMR_ACTTORW3	(3 << (31 - 22))
435 #define LSDMR_ACTTORW7	(7 << (31 - 22))
436 #define LSDMR_ACTTORW6	(6 << (31 - 22))
437 #define LSDMR_BL8	(1 << (31 - 23))
438 #define LSDMR_WRC2	(2 << (31 - 27))
439 #define LSDMR_WRC4	(0 << (31 - 27))
440 #define LSDMR_BUFCMD	(1 << (31 - 29))
441 #define LSDMR_CL3	(3 << (31 - 31))
442 
443 #define LSDMR_OP_NORMAL	(0 << (31 - 4))
444 #define LSDMR_OP_ARFRSH	(1 << (31 - 4))
445 #define LSDMR_OP_SRFRSH	(2 << (31 - 4))
446 #define LSDMR_OP_MRW	(3 << (31 - 4))
447 #define LSDMR_OP_PRECH	(4 << (31 - 4))
448 #define LSDMR_OP_PCHALL	(5 << (31 - 4))
449 #define LSDMR_OP_ACTBNK	(6 << (31 - 4))
450 #define LSDMR_OP_RWINV	(7 << (31 - 4))
451 
452 /* LTESR - Transfer Error Status Register
453  */
454 #define LTESR_BM               0x80000000
455 #define LTESR_FCT              0x40000000
456 #define LTESR_PAR              0x20000000
457 #define LTESR_WP               0x04000000
458 #define LTESR_ATMW             0x00800000
459 #define LTESR_ATMR             0x00400000
460 #define LTESR_CS               0x00080000
461 #define LTESR_CC               0x00000001
462 
463 #ifndef __ASSEMBLY__
464 #include <asm/io.h>
465 
466 extern void print_lbc_regs(void);
467 extern void init_early_memctl_regs(void);
468 extern void upmconfig(uint upm, uint *table, uint size);
469 
470 #define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
471 #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr))
472 #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr))
473 #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
474 #define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
475 #define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
476 #define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
477 
478 typedef struct lbc_bank {
479 	u32     br;
480 	u32     or;
481 } lbc_bank_t;
482 
483 /* Local Bus Controller Registers */
484 typedef struct fsl_lbc {
485 	lbc_bank_t      bank[8];
486 	u8	res1[40];
487 	u32     mar;            /* LBC UPM Addr */
488 	u8      res2[4];
489 	u32     mamr;           /* LBC UPMA Mode */
490 	u32     mbmr;           /* LBC UPMB Mode */
491 	u32     mcmr;           /* LBC UPMC Mode */
492 	u8      res3[8];
493 	u32     mrtpr;          /* LBC Memory Refresh Timer Prescaler */
494 	u32     mdr;            /* LBC UPM Data */
495 #ifdef CONFIG_FSL_ELBC
496 	u8      res4[4];
497 	u32     lsor;
498 	u8      res5[12];
499 	u32     lurt;           /* LBC UPM Refresh Timer */
500 	u8	res6[4];
501 #else
502 	u8	res4[8];
503 	u32     lsdmr;          /* LBC SDRAM Mode */
504 	u8	res5[8];
505 	u32     lurt;           /* LBC UPM Refresh Timer */
506 	u32     lsrt;           /* LBC SDRAM Refresh Timer */
507 #endif
508 	u8      res7[8];
509 	u32     ltesr;          /* LBC Transfer Error Status */
510 	u32     ltedr;          /* LBC Transfer Error Disable */
511 	u32     lteir;          /* LBC Transfer Error IRQ */
512 	u32     lteatr;         /* LBC Transfer Error Attrs */
513 	u32     ltear;          /* LBC Transfer Error Addr */
514 	u8      res8[12];
515 	u32     lbcr;           /* LBC Configuration */
516 	u32     lcrr;           /* LBC Clock Ratio */
517 #ifdef CONFIG_NAND_FSL_ELBC
518 	u8	res9[0x8];
519 	u32     fmr;            /* Flash Mode Register */
520 	u32     fir;            /* Flash Instruction Register */
521 	u32     fcr;            /* Flash Command Register */
522 	u32     fbar;           /* Flash Block Addr Register */
523 	u32     fpar;           /* Flash Page Addr Register */
524 	u32     fbcr;           /* Flash Byte Count Register */
525 	u8      res10[0xF08];
526 #else
527 	u8      res9[0xF28];
528 #endif
529 } fsl_lbc_t;
530 
531 #endif /* __ASSEMBLY__ */
532 #endif /* __ASM_PPC_FSL_LBC_H */
533