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/external/llvm/test/Linker/
Dsubprogram-linkonce-weak.ll2 ; RUN: FileCheck %s -check-prefix=LW -check-prefix=CHECK <%t1
16 ; The LW prefix means linkonce (this file) first, then weak (the other file).
20 ; LW: define i32 @bar({{.*}} !dbg ![[BARSP:[0-9]+]]
21 ; LW: %sum = add i32 %a, %b, !dbg ![[FOOINBAR:[0-9]+]]
22 ; LW: ret i32 %sum, !dbg ![[BARRET:[0-9]+]]
23 ; LW: define weak i32 @foo({{.*}} !dbg ![[WEAKFOOSP:[0-9]+]]
24 ; LW: %sum = call i32 @fastadd(i32 %a, i32 %b), !dbg ![[FOOCALL:[0-9]+]]
25 ; LW: ret i32 %sum, !dbg ![[FOORET:[0-9]+]]
52 ; LW-SAME: !{![[LCU:[0-9]+]], ![[WCU:[0-9]+]]}
56 ; LW: ![[LCU]] = distinct !DICompileUnit(
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Linker/
Dsubprogram-linkonce-weak.ll2 ; RUN: FileCheck %s -check-prefix=LW -check-prefix=CHECK <%t1
16 ; The LW prefix means linkonce (this file) first, then weak (the other file).
20 ; LW: define i32 @bar({{.*}} !dbg ![[BARSP:[0-9]+]]
21 ; LW: %sum = add i32 %a, %b, !dbg ![[FOOINBAR:[0-9]+]]
22 ; LW: ret i32 %sum, !dbg ![[BARRET:[0-9]+]]
23 ; LW: define weak i32 @foo({{.*}} !dbg ![[WEAKFOOSP:[0-9]+]]
24 ; LW: %sum = call i32 @fastadd(i32 %a, i32 %b), !dbg ![[FOOCALL:[0-9]+]]
25 ; LW: ret i32 %sum, !dbg ![[FOORET:[0-9]+]]
52 ; LW-SAME: !{![[LCU:[0-9]+]], ![[WCU:[0-9]+]]}
56 ; LW: ![[LCU]] = distinct !DICompileUnit(
[all …]
/external/libffi/src/tile/
Dtile.S48 #define LW ld macro
52 #define LW lw macro
139 LW TMP, INCOMING_STACK_ARGS
159 LW r0, r0
165 LW REG, PTR ; \
186 LW lr, r52
192 LW RETURN_REG_ADDR, TMP
201 LW r52, TMP
311 LW lr, r10
/external/python/cpython2/Modules/_ctypes/libffi/src/tile/
Dtile.S48 #define LW ld macro
52 #define LW lw macro
139 LW TMP, INCOMING_STACK_ARGS
159 LW r0, r0
165 LW REG, PTR ; \
186 LW lr, r52
192 LW RETURN_REG_ADDR, TMP
201 LW r52, TMP
311 LW lr, r10
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dpointers.mir23 ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[COPY]], 0 :: (load 4 from %ir.p)
24 ; MIPS32: $v0 = COPY [[LW]]
47 ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 0)
48 ; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[LW]], 0 :: (load 4 from %ir.p)
Dstack_args.mir28 ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDiu]], 0 :: (load 4 from %fixed-stack.0, align 0)
38 ; MIPS32: SW [[LW]], [[ADDu]], 0 :: (store 4 into stack + 16, align 0)
/external/libvpx/libvpx/third_party/libyuv/include/libyuv/
Dmacros_msa.h19 #define LW(psrc) \ macro
45 val0_m = LW(psrc_ld_m); \
46 val1_m = LW(psrc_ld_m + 4); \
84 #define LW(psrc) \ macro
110 val0_m = LW(psrc_ld_m); \
111 val1_m = LW(psrc_ld_m + 4); \
/external/libyuv/files/include/libyuv/
Dmacros_msa.h19 #define LW(psrc) \ macro
45 val0_m = LW(psrc_ld_m); \
46 val1_m = LW(psrc_ld_m + 4); \
84 #define LW(psrc) \ macro
110 val0_m = LW(psrc_ld_m); \
111 val1_m = LW(psrc_ld_m + 4); \
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/mirparser/
Dtarget-flags-pic-o32.mir78 %2 = LW %1, target-flags(mips-got-call) @_Z1gi :: (load 4 from call-entry @_Z1gi)
85 %5 = LW %1, target-flags(mips-got) @v :: (load 4 from got)
86 %6 = LW killed %5, 0 :: (dereferenceable load 4 from @v)
88 %8 = LW %1, target-flags(mips-got) @j :: (load 4 from got)
89 %9 = LW killed %8, 0 :: (dereferenceable load 4 from @j)
Dtarget-flags-pic.mir89 %7 = LW killed %6, 0 :: (dereferenceable load 4 from @v)
92 %10 = LW killed %9, 0 :: (dereferenceable load 4 from @j)
Dtarget-flags-static-tls.mir156 %14 = LW killed %13, target-flags(mips-abs-lo) @v :: (dereferenceable load 4 from @v)
177 %1 = LW killed %36, 0 :: (dereferenceable load 4 from @k)
230 %48 = LW killed %47, 0 :: (dereferenceable load 4 from @j)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/micromips-sizereduction/
Dmicromips-lwp-swp.mir78 $s0 = LW $sp, 20 :: (load 4 from %stack.2)
79 $s1 = LW $sp, 24 :: (load 4 from %stack.1)
80 $ra = LW $sp, 28 :: (load 4 from %stack.0)
148 $ra = LW $sp, 28 :: (load 4 from %stack.0)
215 $s1 = LW $sp, 24 :: (load 4 from %stack.1)
216 $ra = LW $sp, 28 :: (load 4 from %stack.0)
282 $s0 = LW $sp, 20 :: (load 4 from %stack.2)
284 $ra = LW $sp, 28 :: (load 4 from %stack.0)
Dmicromips-no-lwp-swp.mir69 $s0 = LW $sp, 16 :: (load 4 from %stack.1)
70 $ra = LW $sp, 20 :: (load 4 from %stack.0)
188 $ra = LW $sp, 20 :: (load 4 from %stack.0)
246 $s0 = LW $sp, 16 :: (load 4 from %stack.1)
/external/libpng/mips/
Dfilter_msa_intrinsics.c44 #define LW(psrc) \ macro
115 #define LW(psrc) \ macro
183 #define LW(psrc) \ macro
471 inp0 = LW(src); in png_read_filter_row_sub4_msa()
512 inp0 = LW(src); in png_read_filter_row_sub3_msa()
553 inp0 = LW(pp); in png_read_filter_row_avg4_msa()
555 inp1 = LW(src); in png_read_filter_row_avg4_msa()
608 inp0 = LW(pp); in png_read_filter_row_avg3_msa()
610 inp1 = LW(src); in png_read_filter_row_avg3_msa()
669 inp0 = LW(nxt); in png_read_filter_row_paeth4_msa()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsEmitGPRestore.cpp67 BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI) in runOnMachineFunction()
80 BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI) in runOnMachineFunction()
/external/libaom/libaom/aom_dsp/mips/
Dintrapred_msa.c26 src_data = LW(src); in intra_predict_vert_4x4_msa()
36 src_data1 = LW(src); in intra_predict_vert_8x8_msa()
37 src_data2 = LW(src + 4); in intra_predict_vert_8x8_msa()
164 val0 = LW(src_top); in intra_predict_dc_4x4_msa()
165 val1 = LW(src_left); in intra_predict_dc_4x4_msa()
184 val0 = LW(src); in intra_predict_dc_tl_4x4_msa()
/external/clang/utils/ABITest/
DEnumeration.py150 LW,RW = W//2, W - (W//2)
151 L,R = getNthPairBounded(N, H**LW, H**RW)
152 return (getNthNTuple(L,LW,H=H,useLeftToRight=useLeftToRight) +
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/longbranch/
Dbranch-limits-int-micromipsr6.mir204 ; PIC: $ra = LW $sp, 0
291 ; PIC: $ra = LW $sp, 0
378 ; PIC: $ra = LW $sp, 0
465 ; PIC: $ra = LW $sp, 0
552 ; PIC: $ra = LW $sp, 0
639 ; PIC: $ra = LW $sp, 0
726 ; PIC: $ra = LW $sp, 0
813 ; PIC: $ra = LW $sp, 0
900 ; PIC: $ra = LW $sp, 0
987 ; PIC: $ra = LW $sp, 0
[all …]
Dbranch-limits-int-mipsr6.mir204 ; PIC: $ra = LW $sp, 0
291 ; PIC: $ra = LW $sp, 0
378 ; PIC: $ra = LW $sp, 0
465 ; PIC: $ra = LW $sp, 0
552 ; PIC: $ra = LW $sp, 0
639 ; PIC: $ra = LW $sp, 0
726 ; PIC: $ra = LW $sp, 0
813 ; PIC: $ra = LW $sp, 0
900 ; PIC: $ra = LW $sp, 0
987 ; PIC: $ra = LW $sp, 0
[all …]
Dbranch-limits-int-microMIPS.mir163 ; PIC: $ra = LW $sp, 0
258 ; PIC: $ra = LW $sp, 0
353 ; PIC: $ra = LW $sp, 0
448 ; PIC: $ra = LW $sp, 0
543 ; PIC: $ra = LW $sp, 0
634 ; PIC: $ra = LW $sp, 0
729 ; PIC: $ra = LW $sp, 0
824 ; PIC: $ra = LW $sp, 0
Dbranch-limits-int.mir147 ; PIC: $ra = LW $sp, 0
246 ; PIC: $ra = LW $sp, 0
345 ; PIC: $ra = LW $sp, 0
444 ; PIC: $ra = LW $sp, 0
543 ; PIC: $ra = LW $sp, 0
642 ; PIC: $ra = LW $sp, 0
/external/libvpx/libvpx/vpx_dsp/mips/
Dintrapred_msa.c24 src_data = LW(src); in intra_predict_vert_4x4_msa()
34 src_data1 = LW(src); in intra_predict_vert_8x8_msa()
35 src_data2 = LW(src + 4); in intra_predict_vert_8x8_msa()
162 val0 = LW(src_top); in intra_predict_dc_4x4_msa()
163 val1 = LW(src_left); in intra_predict_dc_4x4_msa()
182 val0 = LW(src); in intra_predict_dc_tl_4x4_msa()
394 val = LW(src_top_ptr); in intra_predict_tm_4x4_msa()
/external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/MIR/Mips/
Dlast-inst-bundled.mir171 …renamable $at = LW $sp, 20, debug-location !21 :: (dereferenceable load 4 from %ir.condition, !tba…
185 $s0 = LW $sp, 24, debug-location !29 :: (load 4 from %stack.2)
186 $ra = LW $sp, 28, debug-location !29 :: (load 4 from %stack.1)
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h43 #define LW(psrc) \ macro
76 val0_m = LW(psrc_m); \
77 val1_m = LW(psrc_m + 4); \
120 #define LW(psrc) \ macro
153 val0_m = LW(psrc_m1); \
154 val1_m = LW(psrc_m1 + 4); \
208 out0 = LW((psrc)); \
209 out1 = LW((psrc) + stride); \
210 out2 = LW((psrc) + 2 * stride); \
211 out3 = LW((psrc) + 3 * stride); \
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMipsSizeReduction.cpp236 {RT_TwoInstr, OpCodes(Mips::LW, Mips::LWP_MM), ReduceXWtoXWP,
238 {RT_OneInstr, OpCodes(Mips::LW, Mips::LWSP_MM), ReduceXWtoXWSP,
349 !(MI->getOpcode() == Mips::LW || MI->getOpcode() == Mips::LW_MM || in CheckXWPInstr()
462 bool ReduceToLwp = (MI1->getOpcode() == Mips::LW) || in ReduceXWtoXWP()

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