Home
last modified time | relevance | path

Searched refs:LZCNT (Results 1 – 25 of 29) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopIdiom/X86/
Dctlz.ll1 ; RUN: opt -loop-idiom -mtriple=x86_64 -mcpu=core-avx2 < %s -S | FileCheck -check-prefix=LZCNT --ch…
19 ; LZCNT: entry
20 ; LZCNT: %0 = call i32 @llvm.ctlz.i32(i32 %shr8, i1 true)
21 ; LZCNT-NEXT: %1 = sub i32 32, %0
22 ; LZCNT-NEXT: %2 = zext i32 %1 to i64
23 ; LZCNT: %indvars.iv.next.lcssa = phi i64 [ %2, %while.body ]
24 ; LZCNT: %4 = trunc i64 %indvars.iv.next.lcssa to i32
25 ; LZCNT: %i.0.lcssa = phi i32 [ 0, %entry ], [ %4, %while.end.loopexit ]
26 ; LZCNT: ret i32 %i.0.lcssa
416 ; LZCNT-LABEL: @foo(
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopIdiom/ARM/
Dctlz.ll1 ; RUN: opt -loop-idiom -mtriple=armv7a < %s -S | FileCheck -check-prefix=LZCNT --check-prefix=ALL %s
19 ; LZCNT: entry
20 ; LZCNT: %0 = call i32 @llvm.ctlz.i32(i32 %shr8, i1 true)
21 ; LZCNT-NEXT: %1 = sub i32 32, %0
22 ; LZCNT-NEXT: %2 = zext i32 %1 to i64
23 ; LZCNT: %indvars.iv.next.lcssa = phi i64 [ %2, %while.body ]
24 ; LZCNT: %4 = trunc i64 %indvars.iv.next.lcssa to i32
25 ; LZCNT: %i.0.lcssa = phi i32 [ 0, %entry ], [ %4, %while.end.loopexit ]
26 ; LZCNT: ret i32 %i.0.lcssa
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll2 …le=x86_64-unknown-unknown -mattr=+lzcnt < %s | FileCheck %s --check-prefix=ALL --check-prefix=LZCNT
134 ; LZCNT-NOT: select
157 ; LZCNT-NOT: select
179 ; LZCNT-NEXT: select i1 [[COND]], i64 32, i64 [[ZEXT]]
202 ; LZCNT-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
225 ; LZCNT-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
248 ; LZCNT-NEXT: select i1 [[COND]], i16 32, i16 [[TRUNC]]
272 ; LZCNT-NOT: select
295 ; LZCNT-NOT: select
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll2 …le=x86_64-unknown-unknown -mattr=+lzcnt < %s | FileCheck %s --check-prefix=ALL --check-prefix=LZCNT
134 ; LZCNT-NOT: select
157 ; LZCNT-NOT: select
179 ; LZCNT-NEXT: select i1 [[COND]], i64 32, i64 [[ZEXT]]
202 ; LZCNT-NEXT: select i1 [[COND]], i32 64, i32 [[TRUNC]]
225 ; LZCNT-NEXT: select i1 [[COND]], i16 64, i16 [[TRUNC]]
248 ; LZCNT-NEXT: select i1 [[COND]], i16 32, i16 [[TRUNC]]
272 ; LZCNT-NOT: select
295 ; LZCNT-NOT: select
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-mca/X86/BtVer2/
Dclear-super-register-1.s11 ## The AND can start immediately after the LZCNT.
/external/v8/src/x64/
Dmacro-assembler-x64.cc1652 if (CpuFeatures::IsSupported(LZCNT)) { in Lzcntl()
1653 CpuFeatureScope scope(this, LZCNT); in Lzcntl()
1666 if (CpuFeatures::IsSupported(LZCNT)) { in Lzcntl()
1667 CpuFeatureScope scope(this, LZCNT); in Lzcntl()
1680 if (CpuFeatures::IsSupported(LZCNT)) { in Lzcntq()
1681 CpuFeatureScope scope(this, LZCNT); in Lzcntq()
1694 if (CpuFeatures::IsSupported(LZCNT)) { in Lzcntq()
1695 CpuFeatureScope scope(this, LZCNT); in Lzcntq()
Dassembler-x64.cc100 if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT; in ProbeImpl()
120 CpuFeatures::IsSupported(LZCNT), CpuFeatures::IsSupported(POPCNT), in PrintFeatures()
4467 DCHECK(IsEnabled(LZCNT)); in lzcntq()
4477 DCHECK(IsEnabled(LZCNT)); in lzcntq()
4488 DCHECK(IsEnabled(LZCNT)); in lzcntl()
4498 DCHECK(IsEnabled(LZCNT)); in lzcntl()
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/
Disa.hpp92 bool LZCNT(void) { return CPU_Rep.isIntel_ && CPU_Rep.f_81_ECX_[5]; } in LZCNT() function in InstructionSet
/external/llvm/test/CodeGen/X86/
Dlzcnt-tzcnt.ll3 ; LZCNT and TZCNT will always produce the operand size when the input operand
4 ; is zero. This test is to verify that we efficiently select LZCNT/TZCNT
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dlzcnt-tzcnt.ll4 ; LZCNT and TZCNT will always produce the operand size when the input operand
5 ; is zero. This test is to verify that we efficiently select LZCNT/TZCNT
Dclz.ll705 ; FIXME: We should probably select BSR instead of LZCNT in these circumstances.
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86.td106 "Support LZCNT instruction">;
DX86GenSubtargetInfo.inc69 { "lzcnt", "Support LZCNT instruction", X86::FeatureLZCNT, 0ULL },
DX86InstrInfo.td1348 // LZCNT Instruction
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86.td207 "Support LZCNT instruction">;
284 "LZCNT/TZCNT have a false dependency on dest register">;
317 "LZCNT instructions are as fast as most simple integer ops">;
/external/llvm/lib/Target/Sparc/
DSparcInstrVIS.td242 def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrVIS.td242 def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
/external/v8/src/ia32/
Dmacro-assembler-ia32.cc1547 if (CpuFeatures::IsSupported(LZCNT)) { in Lzcnt()
1548 CpuFeatureScope scope(this, LZCNT); in Lzcnt()
Dassembler-ia32.cc148 if (cpu.has_lzcnt() && FLAG_enable_lzcnt) supported_ |= 1u << LZCNT; in ProbeImpl()
166 CpuFeatures::IsSupported(BMI2), CpuFeatures::IsSupported(LZCNT), in PrintFeatures()
3068 DCHECK(IsEnabled(LZCNT)); in lzcnt()
/external/v8/src/
Dglobals.h804 LZCNT, enumerator
/external/llvm/lib/Target/X86/
DX86.td181 "Support LZCNT instruction">;
DX86SchedHaswell.td876 // LZCNT TZCNT.
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dnacl-other-intrinsics.ll456 ; TODO(jvoung): If we detect that LZCNT is supported, then use that
/external/capstone/arch/Sparc/
DSparcGenDisassemblerTables.inc924 /* 3661 */ MCD_OPC_Decode, 195, 2, 47, // Opcode: LZCNT
/external/syzkaller/pkg/ifuzz/gen/
Dall-enc-instructions.txt15568 # LZCNT reg16, reg/mem16 F30FBD /r
15569 # LZCNT reg32, reg/mem32 F30FBD /r
15570 # LZCNT reg64, reg/mem64 F30FBD /r
15573 ICLASS : LZCNT
15588 COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replac…
24967 # LZCNT reg16, reg/mem16 F30FBD /r
24968 # LZCNT reg32, reg/mem32 F30FBD /r
24969 # LZCNT reg64, reg/mem64 F30FBD /r
24972 ICLASS : LZCNT
24973 # This replace the AMD version in LZCNT builds
[all …]

12