| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.h | 74 unsigned Lanes; variable
80 void setLanes(unsigned l) { Lanes = l; }; in setLanes()
90 unsigned getLanes() const { return (Lanes); }; in getLanes()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.h | 82 unsigned Lanes; variable
88 void setLanes(unsigned l) { Lanes = l; } in setLanes()
99 unsigned getLanes() const { return Lanes; } in getLanes()
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| D | HexagonShuffler.cpp | 168 unsigned Lanes; member
172 static unsigned makeAllBits(unsigned startBit, unsigned Lanes) in makeAllBits() argument
174 for (unsigned i = 1; i < Lanes; ++i) in makeAllBits()
187 unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes); in checkHVXPipes()
588 inst.Lanes = I->CVI.getLanes(); in check()
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| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 160 // Vector Add Across Lanes
165 // Vector Long Add Across Lanes
256 // Vector Max Across Lanes
272 // Vector Min Across Lanes
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 162 // Vector Add Across Lanes
167 // Vector Long Add Across Lanes
258 // Vector Max Across Lanes
274 // Vector Min Across Lanes
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | O3-pipeline.ll | 100 ; CHECK-NEXT: Detect Dead Lanes
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | O3-pipeline.ll | 96 ; CHECK-NEXT: Detect Dead Lanes
|
| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1995 LaneBitmask Lanes = SubRangeJoin ? 1 : TRI->getSubRegIndexLaneMask(SubIdx); in analyzeValue() local
1996 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
2297 LaneBitmask Lanes) const { in usesLanes()
2305 if (Lanes & TRI->getSubRegIndexLaneMask( in usesLanes()
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| /external/u-boot/board/freescale/t4qds/ |
| D | README | 84 four Lanes A/B/C/D to a SFP+ cages, which to house fiber cable or
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 2353 LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0) in analyzeValue() local
2355 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
2659 LaneBitmask Lanes) const { in usesLanes()
2668 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any()) in usesLanes()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 382 # Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 360 # Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef.
|
| /external/v8/src/mips/ |
| D | simulator-mips.cc | 5671 #define MSA_3RF_DF(T1, T2, Lanes, ws, wt, wd) \ in DecodeTypeMsa3RF() argument
5672 for (int i = 0; i < Lanes; i++) { \ in DecodeTypeMsa3RF()
5675 #define MSA_3RF_DF2(T1, T2, Lanes, ws, wt, wd) \ in DecodeTypeMsa3RF() argument
5676 for (int i = 0; i < Lanes; i++) { \ in DecodeTypeMsa3RF()
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| /external/v8/src/mips64/ |
| D | simulator-mips64.cc | 5895 #define MSA_3RF_DF(T1, T2, Lanes, ws, wt, wd) \ in DecodeTypeMsa3RF() argument
5896 for (int i = 0; i < Lanes; i++) { \ in DecodeTypeMsa3RF()
5899 #define MSA_3RF_DF2(T1, T2, Lanes, ws, wt, wd) \ in DecodeTypeMsa3RF() argument
5900 for (int i = 0; i < Lanes; i++) { \ in DecodeTypeMsa3RF()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorize.cpp | 2072 unsigned Lanes = in buildScalarSteps() local
2077 for (unsigned Lane = 0; Lane < Lanes; ++Lane) { in buildScalarSteps()
3842 unsigned Lanes = Cost->isUniformAfterVectorization(P, VF) ? 1 : VF; in widenPHIInstruction() local
3846 for (unsigned Lane = 0; Lane < Lanes; ++Lane) { in widenPHIInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 10803 SmallVector<int, 4> Lanes((unsigned)NumLanes, -1); in lowerVectorShuffleByMerging128BitLanes() local
10811 if (Lanes[j] < 0) { in lowerVectorShuffleByMerging128BitLanes()
10813 Lanes[j] = Mask[i] / LaneSize; in lowerVectorShuffleByMerging128BitLanes()
10814 } else if (Lanes[j] != Mask[i] / LaneSize) { in lowerVectorShuffleByMerging128BitLanes()
10834 if (Lanes[i] >= 0) { in lowerVectorShuffleByMerging128BitLanes()
10835 LaneMask[2 * i + 0] = 2*Lanes[i] + 0; in lowerVectorShuffleByMerging128BitLanes()
10836 LaneMask[2 * i + 1] = 2*Lanes[i] + 1; in lowerVectorShuffleByMerging128BitLanes()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 13272 SmallVector<int, 4> Lanes((unsigned)NumLanes, -1); in lowerVectorShuffleByMerging128BitLanes() local
13280 if (Lanes[j] < 0) { in lowerVectorShuffleByMerging128BitLanes()
13282 Lanes[j] = Mask[i] / LaneSize; in lowerVectorShuffleByMerging128BitLanes()
13283 } else if (Lanes[j] != Mask[i] / LaneSize) { in lowerVectorShuffleByMerging128BitLanes()
13303 if (Lanes[i] >= 0) { in lowerVectorShuffleByMerging128BitLanes()
13304 LaneMask[2 * i + 0] = 2*Lanes[i] + 0; in lowerVectorShuffleByMerging128BitLanes()
13305 LaneMask[2 * i + 1] = 2*Lanes[i] + 1; in lowerVectorShuffleByMerging128BitLanes()
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| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | 2013-1_UNLOCODE_CodeListPart3.csv | 13330 ,"US","XL4","Cross Lanes","Cross Lanes","WV","--3--6--","RL","1207",,"3825N 08147W",
|