Home
last modified time | relevance | path

Searched refs:Latency (Results 1 – 25 of 456) sorted by relevance

12345678910>>...19

/external/v8/src/compiler/mips64/
Dinstruction-scheduler-mips64.cc327 enum Latency { enum
490 return Latency::MUL; in MulLatency()
492 return Latency::MUL + 1; in MulLatency()
499 latency = Latency::DMUL; in DmulLatency()
501 latency = Latency::DMULT + Latency::MFLO; in DmulLatency()
512 latency = Latency::MUH; in MulhLatency()
514 latency = Latency::MULT + Latency::MFHI; in MulhLatency()
525 latency = Latency::MUH; in MulhuLatency()
527 latency = Latency::MULTU + Latency::MFHI; in MulhuLatency()
538 latency = Latency::DMUH; in DMulhLatency()
[all …]
/external/v8/src/compiler/mips/
Dinstruction-scheduler-mips.cc298 enum Latency { enum
431 return (6 + 2 * Latency::BRANCH); in ClzLatency()
476 return Latency::MULT + 1; in MulLatency()
478 return Latency::MUL + 1; in MulLatency()
482 return Latency::MULT + 2; in MulLatency()
484 return Latency::MUL + 2; in MulLatency()
510 return latency + Latency::BRANCH + 2; in ShlPairLatency()
524 return latency + Latency::BRANCH + 2; in ShrPairLatency()
538 Latency::BRANCH + 6; in SarPairLatency()
591 return latency + Latency::MULTU + 2; in MuluLatency()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMScheduleA57WriteRes.td15 // Latency: #cyc
27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
31 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
33 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
35 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
37 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
39 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57WriteRes.td15 // Latency: #cyc
26 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
31 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
33 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
35 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
36 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
[all …]
DAArch64SchedKryoDetails.td17 let Latency = 3; let NumMicroOps = 2;
24 let Latency = 3; let NumMicroOps = 2;
31 let Latency = 4; let NumMicroOps = 3;
37 let Latency = 4; let NumMicroOps = 4;
43 let Latency = 3; let NumMicroOps = 4;
49 let Latency = 3; let NumMicroOps = 2;
55 let Latency = 3; let NumMicroOps = 2;
61 let Latency = 3; let NumMicroOps = 2;
67 let Latency = 3; let NumMicroOps = 2;
73 let Latency = 3; let NumMicroOps = 2;
[all …]
DAArch64SchedKryo.td60 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
61 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
63 { let Latency = 2; let NumMicroOps = 2; }
65 { let Latency = 2; let NumMicroOps = 2; }
67 { let Latency = 2; let NumMicroOps = 2; }
68 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
70 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
72 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
73 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
74 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }
[all …]
DAArch64SchedM1.td71 def : WriteRes<WriteBr, [M1UnitB]> { let Latency = 1; }
72 def : WriteRes<WriteBrReg, [M1UnitC]> { let Latency = 1; }
76 def : WriteRes<WriteI, [M1UnitALU]> { let Latency = 1; }
78 def : WriteRes<WriteISReg, [M1UnitALU]> { let Latency = 1; }
79 def : WriteRes<WriteIEReg, [M1UnitALU]> { let Latency = 1; }
80 def : WriteRes<WriteIS, [M1UnitALU]> { let Latency = 1; }
83 def : WriteRes<WriteImm, [M1UnitALU]> { let Latency = 1; }
87 def : WriteRes<WriteID32, [M1UnitC]> { let Latency = 13; }
88 def : WriteRes<WriteID64, [M1UnitC]> { let Latency = 21; }
91 def : WriteRes<WriteIM32, [M1UnitC]> { let Latency = 3; }
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedA57WriteRes.td15 // Latency: #cyc
26 def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
27 def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28 def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29 def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
31 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
33 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
35 def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
36 def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
[all …]
DAArch64SchedKryoDetails.td17 let Latency = 3; let NumMicroOps = 2;
24 let Latency = 3; let NumMicroOps = 2;
31 let Latency = 4; let NumMicroOps = 3;
37 let Latency = 4; let NumMicroOps = 4;
43 let Latency = 3; let NumMicroOps = 4;
49 let Latency = 3; let NumMicroOps = 2;
55 let Latency = 3; let NumMicroOps = 2;
61 let Latency = 3; let NumMicroOps = 2;
67 let Latency = 3; let NumMicroOps = 2;
73 let Latency = 3; let NumMicroOps = 2;
[all …]
DAArch64SchedKryo.td65 def : WriteRes<WriteImm, [KryoUnitXY]> { let Latency = 1; }
66 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
68 { let Latency = 2; let NumMicroOps = 2; }
70 { let Latency = 2; let NumMicroOps = 2; }
72 { let Latency = 2; let NumMicroOps = 2; }
73 def : WriteRes<WriteIS, [KryoUnitXY]> { let Latency = 2; }
75 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
77 { let Latency = 8; let NumMicroOps = 1; } // Fragent -1
78 def : WriteRes<WriteIM32, [KryoUnitX]> { let Latency = 5; }
79 def : WriteRes<WriteIM64, [KryoUnitX]> { let Latency = 5; }
[all …]
DAArch64SchedExynosM1.td74 def M1WriteA1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
75 def M1WriteA2 : SchedWriteRes<[M1UnitALU]> { let Latency = 2; }
76 def M1WriteAA : SchedWriteRes<[M1UnitALU]> { let Latency = 2;
79 M1UnitC]> { let Latency = 1;
83 M1UnitC]> { let Latency = 2;
86 M1UnitC]> { let Latency = 2;
90 def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; }
91 def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; }
93 def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
97 def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCScheduleE5500.td53 [5, 2, 2], // Latency = 1
58 [5, 2, 2], // Latency = 1
63 [5, 2, 2, 2], // Latency = 1
69 [6, 2, 2], // Latency = 1 or 2
75 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
81 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
86 [11], // Latency = 7, Repeat rate = 1
90 [11, 2, 2], // Latency = 7, Repeat rate = 7
95 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
101 [8, 2, 2], // Latency = 4, Repeat rate = 1
[all …]
DPPCScheduleE500.td44 [4, 1, 1], // Latency = 1
49 [4, 1, 1], // Latency = 1
54 [4, 1, 1, 1], // Latency = 1
60 [5, 1, 1], // Latency = 1 or 2
66 [17, 1, 1], // Latency=4..35, Repeat= 4..35
71 [7, 1, 1], // Latency = 4, Repeat rate = 1
76 [7, 1, 1], // Latency = 4, Repeat rate = 1
81 [7, 1, 1], // Latency = 4, Repeat rate = 1
86 [4, 1, 1], // Latency = 1
91 [4, 1, 1], // Latency = 1
[all …]
DPPCScheduleE500mc.td49 [4, 1, 1], // Latency = 1
54 [4, 1, 1], // Latency = 1
59 [4, 1, 1, 1], // Latency = 1
65 [5, 1, 1], // Latency = 1 or 2
71 [17, 1, 1], // Latency=4..35, Repeat= 4..35
76 [11], // Latency = 8
80 [11, 1, 1], // Latency = 8
84 [7, 1, 1], // Latency = 4, Repeat rate = 1
89 [7, 1, 1], // Latency = 4, Repeat rate = 1
94 [7, 1, 1], // Latency = 4, Repeat rate = 1
[all …]
DPPCScheduleP9.td117 let Latency = 1;
123 let Latency = 1;
128 let Latency = 1;
133 let Latency = 1;
138 let Latency = 1;
148 let Latency = 2;
152 let Latency = 2;
156 let Latency = 2;
160 let Latency = 3;
164 let Latency = 3;
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCScheduleE5500.td53 [5, 2, 2], // Latency = 1
58 [5, 2, 2], // Latency = 1
63 [5, 2, 2, 2], // Latency = 1
69 [6, 2, 2], // Latency = 1 or 2
75 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
81 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
86 [11], // Latency = 7, Repeat rate = 1
90 [11, 2, 2], // Latency = 7, Repeat rate = 7
95 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
101 [8, 2, 2], // Latency = 4, Repeat rate = 1
[all …]
DPPCScheduleE500mc.td49 [4, 1, 1], // Latency = 1
54 [4, 1, 1], // Latency = 1
59 [4, 1, 1, 1], // Latency = 1
65 [5, 1, 1], // Latency = 1 or 2
71 [17, 1, 1], // Latency=4..35, Repeat= 4..35
76 [11], // Latency = 8
80 [11, 1, 1], // Latency = 8
84 [7, 1, 1], // Latency = 4, Repeat rate = 1
89 [7, 1, 1], // Latency = 4, Repeat rate = 1
94 [7, 1, 1], // Latency = 4, Repeat rate = 1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dmisched-fp-basic.ll19 ; CHECK_A9: Latency : 5
20 ; CHECK_SWIFT: Latency : 4
21 ; CHECK_R52: Latency : 6
26 ; CHECK_SWIFT: Latency : 4
27 ; CHECK_A9: Latency : 6
28 ; CHECK_R52: Latency : 6
31 ; CHECK_SWIFT: Latency : 17
32 ; CHECK_A9: Latency : 16
33 ; CHECK_R52: Latency : 7
36 ; CHECK_SWIFT: Latency : 4
[all …]
Dmisched-int-basic-thumb2.mir41 # CHECK_A9: Latency : 2
42 # CHECK_SWIFT: Latency : 2
43 # CHECK_R52: Latency : 2
46 # CHECK_A9: Latency : 1
47 # CHECK_SWIFT: Latency : 3
48 # CHECK_R52: Latency : 4
51 # CHECK_A9: Latency : 1
52 # CHECK_SWIFT: Latency : 1
53 # CHECK_R52: Latency : 3
56 # CHECK_A9: Latency : 0
[all …]
Dcortex-a57-misched-vfma.ll12 ; CHECK: Latency : 5
16 ; CHECK-SAME: Latency=0
21 ; CHECK: Latency : 9
25 ; CHECK-SAME: Latency=4
29 ; CHECK: Latency : 9
33 ; CHECK-SAME: Latency=9
51 ; CHECK: Latency : 5
55 ; CHECK-SAME: Latency=0
60 ; CHECK: Latency : 9
64 ; CHECK-SAME: Latency=4
[all …]
Dmisched-int-basic.mir32 # CHECK_A9: Latency : 2
33 # CHECK_SWIFT: Latency : 4
34 # CHECK_R52: Latency : 4
37 # CHECK_A9: Latency : 2
38 # CHECK_SWIFT: Latency : 4
39 # CHECK_R52: Latency : 4
42 # CHECK_A9: Latency : 1
43 # CHECK_SWIFT: Latency : 1
44 # CHECK_R52: Latency : 3
47 # CHECK_A9: Latency : 2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86SchedHaswell.td95 let Latency = Lat;
103 let Latency = !add(Lat, LoadLat);
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
149 let Latency = 2;
420 let Latency = 2;
425 let Latency = 6;
431 let Latency = 2;
435 let Latency = 2;
443 let Latency = 11;
448 let Latency = 17;
[all …]
DX86SchedSkylakeClient.td89 let Latency = Lat;
97 let Latency = !add(Lat, LoadLat);
127 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
135 let Latency = 2;
369 let Latency = 2;
374 let Latency = 6;
380 let Latency = 3;
384 let Latency = 2;
434 let Latency = 10;
439 let Latency = 16;
[all …]
DX86SchedBroadwell.td90 let Latency = Lat;
98 let Latency = !add(Lat, LoadLat);
126 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
136 let Latency = 2;
377 let Latency = 2;
382 let Latency = 6;
387 let Latency = 2;
391 let Latency = 2;
441 let Latency = 11;
446 let Latency = 16;
[all …]
/external/llvm/lib/Target/X86/
DX86ScheduleBtVer2.td12 // Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
81 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
86 let Latency = !add(Lat, 3);
94 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
99 let Latency = !add(Lat, 5);
114 let Latency = 6;
120 let Latency = 25;
124 let Latency = 41;
143 def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
178 let Latency = 21;
[all …]

12345678910>>...19