Searched refs:LoHalf (Results 1 – 4 of 4) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAGHVX.cpp | 626 return OpRef(R.OpN & (Undef | Index | LoHalf)); in lo()
646 LoHalf = 0x20000000, enumerator
648 Whole = LoHalf | HiHalf,
720 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); in print()
721 if (OpN & LoHalf) in print()
1006 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); in materialize()
1009 unsigned Sub = (Part == OpRef::LoHalf) ? Hexagon::vsub_lo in materialize()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 4264 MachineInstr *LoHalf = in splitScalar64BitAddSub() local
4288 legalizeOperands(*LoHalf); in splitScalar64BitAddSub()
4330 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp() local
4355 legalizeOperands(LoHalf); in splitScalar64BitBinaryOp()
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| D | SIISelLowering.cpp | 4218 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
4223 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf); in lowerINSERT_VECTOR_ELT()
4237 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf }); in lowerINSERT_VECTOR_ELT()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2784 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp() local
2809 legalizeOperands(LoHalf); in splitScalar64BitBinaryOp()
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