| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUSchedule.td | 20 def LoadStore : InstrItinClass; // ODD_UNIT
41 InstrItinData<LoadStore , [InstrStage<6, [ODD_UNIT]>]>,
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| D | SPUInstrInfo.td | 47 LoadStore,
54 LoadStore,
79 LoadStore,
86 LoadStore,
111 LoadStore,
118 LoadStore,
148 "lqr\t$rT, $disp", LoadStore,
159 LoadStore,
166 LoadStore,
191 LoadStore,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/ |
| D | NVPTX.h | 90 enum LoadStore { enum
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTX.h | 93 enum LoadStore { enum
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Instrumentation/ |
| D | InstrProfiling.cpp | 413 for (const auto &LoadStore : PromotionCandidates) { in promoteCounterLoadStores() local
414 auto *CounterLoad = LoadStore.first; in promoteCounterLoadStores()
415 auto *CounterStore = LoadStore.second; in promoteCounterLoadStores()
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 1168 LoadStore(rt, src, LDRB_w, option); in ldrb()
1177 LoadStore(rt, dst, STRB_w, option); in strb()
1186 LoadStore(rt, src, rt.Is64Bits() ? LDRSB_x : LDRSB_w, option); in ldrsb()
1195 LoadStore(rt, src, LDRH_w, option); in ldrh()
1204 LoadStore(rt, dst, STRH_w, option); in strh()
1213 LoadStore(rt, src, rt.Is64Bits() ? LDRSH_x : LDRSH_w, option); in ldrsh()
1222 LoadStore(rt, src, LoadOpFor(rt), option); in ldr()
1231 LoadStore(rt, dst, StoreOpFor(rt), option); in str()
1241 LoadStore(xt, src, LDRSW_x, option); in ldrsw()
1250 LoadStore(rt, src, LDRB_w, option); in ldurb()
[all …]
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| D | macro-assembler-aarch64.cc | 1905 LoadStore(rt, MemOperand(addr.GetBaseRegister(), temp), op); in LS_MACRO_LIST()
1908 LoadStore(rt, MemOperand(addr.GetBaseRegister()), op); in LS_MACRO_LIST()
1913 LoadStore(rt, MemOperand(addr.GetBaseRegister()), op); in LS_MACRO_LIST()
1916 LoadStore(rt, addr, op); in LS_MACRO_LIST()
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| D | assembler-aarch64.h | 4106 void LoadStore(const CPURegister& rt,
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 1650 LoadStore(rt, src, LDRB_w); in ldrb()
1655 LoadStore(rt, dst, STRB_w); in strb()
1660 LoadStore(rt, src, rt.Is64Bits() ? LDRSB_x : LDRSB_w); in ldrsb()
1665 LoadStore(rt, src, LDRH_w); in ldrh()
1670 LoadStore(rt, dst, STRH_w); in strh()
1675 LoadStore(rt, src, rt.Is64Bits() ? LDRSH_x : LDRSH_w); in ldrsh()
1680 LoadStore(rt, src, LoadOpFor(rt)); in ldr()
1685 LoadStore(rt, src, StoreOpFor(rt)); in str()
1691 LoadStore(rt, src, LDRSW_x); in ldrsw()
4353 void Assembler::LoadStore(const CPURegister& rt, in LoadStore() function in v8::internal::Assembler
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| D | macro-assembler-arm64.cc | 815 LoadStore(rt, MemOperand(addr.base(), temp), op); in LoadStoreMacro()
818 LoadStore(rt, MemOperand(addr.base()), op); in LoadStoreMacro()
823 LoadStore(rt, MemOperand(addr.base()), op); in LoadStoreMacro()
826 LoadStore(rt, addr, op); in LoadStoreMacro()
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| D | assembler-arm64.h | 3221 void LoadStore(const CPURegister& rt,
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