Searched refs:LogicalImm (Results 1 – 5 of 5) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 2541 int64_t LogicalImm = MI.getOperand(2).getImm(); in convertToImmediateForm() local
2544 Result = LogicalImm | SExtImm; in convertToImmediateForm()
2546 Result = LogicalImm ^ SExtImm; in convertToImmediateForm()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 886 defm AND : LogicalImm<0b00, "and", and, "bic">;
887 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
888 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
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| D | AArch64InstrFormats.td | 2087 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
2138 // Split from LogicalImm as not all instructions have both.
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1085 defm AND : LogicalImm<0b00, "and", and, "bic">;
1086 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
1087 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
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| D | AArch64InstrFormats.td | 2445 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
2496 // Split from LogicalImm as not all instructions have both.
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