| /external/vixl/examples/aarch64/ |
| D | simulated-runtime-calls.cc | 68 __ Lsl(w0, w0, 2); in GenerateRuntimeCallExamples() local
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.h | 1049 void Lsl(Register rd, Register rm, const Operand& shift_imm,
1052 void Lsl(Register rd, Register rm, Register rs, Condition cond = AL);
1081 Lsl(reg, reg, Operand(kSmiTagSize), cond);
1085 Lsl(dst, src, Operand(kSmiTagSize), cond);
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| D | assembler_arm.cc | 2602 void Assembler::Lsl(Register rd, Register rm, const Operand& shift_imm,
2610 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
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| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 3437 COMPARE_T32(Lsl(eq, r0, r1, 16), in TEST()
3441 COMPARE_T32(Lsl(eq, r0, r1, 0), in TEST()
3446 COMPARE_T32(Lsl(eq, r0, r1, 32), in TEST()
3452 COMPARE_T32(Lsl(eq, r7, r7, r3), in TEST()
3456 COMPARE_T32(Lsl(eq, r8, r8, r3), in TEST()
4049 CHECK_T32_16(Lsl(DontCare, r0, r1, 31), "lsls r0, r1, #31\n"); in TEST()
4051 CHECK_T32_16_IT_BLOCK(Lsl(DontCare, eq, r0, r1, 31), in TEST()
4055 CHECK_T32_16(Lsl(DontCare, r0, r0, r1), "lsls r0, r1\n"); in TEST()
4057 CHECK_T32_16_IT_BLOCK(Lsl(DontCare, eq, r0, r0, r1), in TEST()
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 144 M(Lsl) \
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 144 M(Lsl) \
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| D | test-assembler-aarch32.cc | 783 __ Lsl(r3, r1, 4); in TEST() local
807 __ Lsl(r3, r1, r9); in TEST() local
2795 __ Lsl(r4, r3, 28); in TEST() local
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 741 void TurboAssembler::Lsl(const Register& rd, const Register& rn, in Lsl() function
748 void TurboAssembler::Lsl(const Register& rd, const Register& rn, in Lsl() function
1034 Lsl(dst, src, kSmiShift); in SmiTag()
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| D | macro-assembler-arm64.h | 909 inline void Lsl(const Register& rd, const Register& rn, unsigned shift);
910 inline void Lsl(const Register& rd, const Register& rn, const Register& rm);
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| /external/v8/src/wasm/baseline/arm64/ |
| D | liftoff-assembler-arm64.h | 406 I32_SHIFTOP(i32_shl, Lsl) in I32_BINOP()
415 I64_SHIFTOP(i64_shl, Lsl) in I32_BINOP()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 398 Lsl, enumerator
1009 using InstARM32Lsl = InstARM32ThreeAddrGPR<InstARM32::Lsl>;
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| D | IceInstARM32.cpp | 3489 template class InstARM32ThreeAddrGPR<InstARM32::Lsl>;
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| /external/v8/src/builtins/arm64/ |
| D | builtins-arm64.cc | 2275 __ Lsl(counter, bound_argc, kPointerSizeLog2); in Generate_PushBoundArguments() local
2995 __ Lsl(result, mantissa, exponent); in Generate_DoubleToI() local
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1140 ASSEMBLE_SHIFT(Lsl, 64); in AssembleArchInstruction()
1143 ASSEMBLE_SHIFT(Lsl, 32); in AssembleArchInstruction()
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 2251 void Lsl(Condition cond, Register rd, Register rm, const Operand& operand) { in Lsl() function
2268 void Lsl(Register rd, Register rm, const Operand& operand) { in Lsl() function
2269 Lsl(al, rd, rm, operand); in Lsl()
2271 void Lsl(FlagsUpdate flags, in Lsl() function
2278 Lsl(cond, rd, rm, operand); in Lsl()
2292 Lsl(cond, rd, rm, operand); in Lsl()
2297 void Lsl(FlagsUpdate flags, in Lsl() function
2301 Lsl(flags, al, rd, rm, operand); in Lsl()
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1904 void Lsl(const Register& rd, const Register& rn, unsigned shift) { in Lsl() function
1911 void Lsl(const Register& rd, const Register& rn, const Register& rm) { in Lsl() function
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 10036 __ Lsl(x16, x0, x1); in TEST() local
10037 __ Lsl(x17, x0, x2); in TEST() local
10038 __ Lsl(x18, x0, x3); in TEST() local
10039 __ Lsl(x19, x0, x4); in TEST() local
10040 __ Lsl(x20, x0, x5); in TEST() local
10041 __ Lsl(x21, x0, x6); in TEST() local
10043 __ Lsl(w22, w0, w1); in TEST() local
10044 __ Lsl(w23, w0, w2); in TEST() local
10045 __ Lsl(w24, w0, w3); in TEST() local
10046 __ Lsl(w25, w0, w4); in TEST() local
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