| /external/v8/src/arm64/ |
| D | deoptimizer-arm64.cc | 205 __ Lsr(unwind_limit, unwind_limit, kPointerSizeLog2); in Generate() local
239 __ Lsr(frame_size, x3, kPointerSizeLog2); in Generate() local
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| D | macro-assembler-arm64-inl.h | 755 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() function
762 void TurboAssembler::Lsr(const Register& rd, const Register& rn, in Lsr() function
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| D | macro-assembler-arm64.h | 921 inline void Lsr(const Register& rd, const Register& rn, unsigned shift);
922 inline void Lsr(const Register& rd, const Register& rn, const Register& rm);
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| /external/v8/src/regexp/arm64/ |
| D | regexp-macro-assembler-arm64.cc | 282 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits); in CheckNotBackReferenceIgnoreCase() local
443 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits); in CheckNotBackReference() local
869 __ Lsr(capture_end.X(), capture_start.X(), kWRegSizeInBits); in GetCode() local
1186 __ Lsr(current_input_offset().X(), GetCachedRegister(reg), in ReadCurrentPositionFromRegister() local
1499 __ Lsr(maybe_result.X(), GetCachedRegister(register_index), in GetRegister() local
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| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 3461 COMPARE_T32(Lsr(eq, r0, r1, 16), in TEST()
3465 COMPARE_T32(Lsr(eq, r0, r1, 32), in TEST()
3469 COMPARE_T32(Lsr(eq, r0, r1, 0), in TEST()
3475 COMPARE_T32(Lsr(eq, r7, r7, r3), in TEST()
3479 COMPARE_T32(Lsr(eq, r8, r8, r3), in TEST()
4061 CHECK_T32_16(Lsr(DontCare, r0, r1, 32), "lsrs r0, r1, #32\n"); in TEST()
4063 CHECK_T32_16_IT_BLOCK(Lsr(DontCare, eq, r0, r1, 32), in TEST()
4067 CHECK_T32_16(Lsr(DontCare, r0, r0, r1), "lsrs r0, r1\n"); in TEST()
4069 CHECK_T32_16_IT_BLOCK(Lsr(DontCare, eq, r0, r0, r1), in TEST()
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| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 146 M(Lsr) \
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| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 146 M(Lsr) \
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| D | test-assembler-aarch32.cc | 784 __ Lsr(r4, r1, 8); in TEST() local
810 __ Lsr(r4, r1, r9); in TEST() local
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| /external/v8/src/wasm/baseline/arm64/ |
| D | liftoff-assembler-arm64.h | 408 I32_SHIFTOP(i32_shr, Lsr) in I32_BINOP()
417 I64_SHIFTOP(i64_shr, Lsr) in I32_BINOP()
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineInternal.h | 528 Value *SimplifyShrShlDemandedBits(Instruction *Lsr, Instruction *Sftl,
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.h | 1054 void Lsr(Register rd, Register rm, const Operand& shift_imm,
1057 void Lsr(Register rd, Register rm, Register rs, Condition cond = AL);
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| D | assembler_arm.cc | 2615 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
2627 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
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| /external/v8/src/builtins/arm64/ |
| D | builtins-arm64.cc | 704 __ Lsr(args_size, args_size, kPointerSizeLog2); in LeaveInterpreterFrame() local
970 __ Lsr(x11, x11, kPointerSizeLog2); in Generate_InterpreterEntryTrampoline() local
3060 __ Lsr(exponent_abs, exponent_abs, 1); in Generate_MathPowInternal() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 399 Lsr, enumerator
1010 using InstARM32Lsr = InstARM32ThreeAddrGPR<InstARM32::Lsr>;
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| D | IceInstARM32.cpp | 3490 template class InstARM32ThreeAddrGPR<InstARM32::Lsr>;
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1146 ASSEMBLE_SHIFT(Lsr, 64); in AssembleArchInstruction()
1149 ASSEMBLE_SHIFT(Lsr, 32); in AssembleArchInstruction()
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 2318 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) { in Lsr() function
2335 void Lsr(Register rd, Register rm, const Operand& operand) { in Lsr() function
2336 Lsr(al, rd, rm, operand); in Lsr()
2338 void Lsr(FlagsUpdate flags, in Lsr() function
2345 Lsr(cond, rd, rm, operand); in Lsr()
2359 Lsr(cond, rd, rm, operand); in Lsr()
2364 void Lsr(FlagsUpdate flags, in Lsr() function
2368 Lsr(flags, al, rd, rm, operand); in Lsr()
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 1919 void Lsr(const Register& rd, const Register& rn, unsigned shift) { in Lsr() function
1926 void Lsr(const Register& rd, const Register& rn, const Register& rm) { in Lsr() function
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| /external/vixl/test/aarch64/ |
| D | test-assembler-aarch64.cc | 10092 __ Lsr(x16, x0, x1); in TEST() local
10093 __ Lsr(x17, x0, x2); in TEST() local
10094 __ Lsr(x18, x0, x3); in TEST() local
10095 __ Lsr(x19, x0, x4); in TEST() local
10096 __ Lsr(x20, x0, x5); in TEST() local
10097 __ Lsr(x21, x0, x6); in TEST() local
10099 __ Lsr(w22, w0, w1); in TEST() local
10100 __ Lsr(w23, w0, w2); in TEST() local
10101 __ Lsr(w24, w0, w3); in TEST() local
10102 __ Lsr(w25, w0, w4); in TEST() local
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